參數(shù)資料
型號： M37920S4CGP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 20 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù)： 19/39頁
文件大?。?/td> 438K
代理商： M37920S4CGP
M37920S4CGP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
26
When ALE expansion wait is selected
W = 0 (0 wait)
W = 1 (1 wait)
W = 2 (2 wait)
tc = 1/f(XIN).
External bus timing
For limits depending on f(XIN), their calculation formulas are shown below.
External clock input
tr
tf
tw(L)
tw(H)
tw(half)
f(XIN)
tc
Test conditions
Vcc = 5 V ± 10 %, Ta = –20 to 85 °C
Input timing voltage : VIL = 1.0 V, VIH = 4.0 V (tw(H), tw(L), tr, tf)
Input timing voltage : 2.5 V (tc, tw(half))
Timing Requirements (VCC = 5 V ± 10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 20 MHz, unless otherwise noted)
ns
50
0.45tc
0.5tc – 8
15
0
0.55tc
8
(2 + W)tc – 45
(1.5 + W)tc – 35
(1 + W)tc – 30
(1 + W)tc – 35
50
0.45tc
0.5tc – 8
15
0
Limits
External clock input cycle time
External clock input pulse width with half input-volage
External clock input high-level pulse width
External clock input low-level pulse width
External clock input rise time
External clock input fall time
Address access time
Chip select access time
Read access time
Read data setup time
Data input hold time after read
Address access time at burst ROM access
Data hold time after address at burst ROM access
Parameter
Max.
Min.
tc
tw(half)
tw(H)
tw(L)
tr
tf
ta(A-D)
ta(CSiL-D)
ta(RDL-D)
tsu(D-RDL)
th(RDH-D)
ta(BA-D)
th(BA-D)
Unit
Symbol
Max.
Min.
When 0/1/2 wait is selected
0.55tc
8
4tc – 45
3.5tc – 35
2tc – 30
2tc – 35
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