參數(shù)資料
型號(hào)： M37920S4CGP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 20 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù)： 25/39頁
文件大?。?/td> 438K
代理商： M37920S4CGP
31
M37920S4CGP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
tw(RASH)
td(CASH-RASH)
th(RASL-CASH)
th(CASL-RASL)
tw(CASL)
td(RA-RASH)
th(RASL-RA)
td(CA-CASH)
th(CASH-CA)
td(WH-CASH)
td(WL-CASH)
th(CASL-WL)
td(D-CASH)
th(CASL-D)
tpxz(CASH-D)
td(CAF-CASH)
td(WFL-CASH)
td(DF-CASH)
tpxz(WH-D)
ta(RASL-D)
ta(CASL-D)
th(CASH-D)
ns
1.5tc – 20
tc – 15
0.5tc – 25
tc – 40
0.5tc – 20
0
3tc – 15
tc – 15
tc – 20
1.5tc – 15
0.5tc + 10
tc – 40
0.5tc – 20
DRAM access
Timing Requirements (VCC = 5 V ± 10 %, VSS = 0 V, Ta = 0 to 70 °C, f(XIN) = 20 MHz, unless otherwise noted)
Limits
RAS access time
CAS access time
Data input hold time after CAS
Parameter
Max.
Min.
Unit
Symbol
ns
0
2.5tc – 35
tc – 30
Limits
RAS high-level pulse width
CAS high-level valid time before RAS
CAS high-level hold time after RAS’s low level
RAS hold time after CAS’s low level
CAS low-level pulse width
Row address valid time before RAS
Row address hold time after RAS’s low level
Column address valid time before CAS
Column address hold time after CAS’s high level
W high-level valid time before CAS
W low-level valid time before CAS
W hold time after CAS’s low level
Data output valid time before CAS
Data output hold time after CAS’s low level
Floating start delay time after CAS
Column address valid time before CAS (When fast page access ON is selected)
W low-level valid time before CAS (When fast page access ON is selected)
Data output valid time before CAS (When fast page access ON is selected)
Floating start delay time after write
Parameter
Max.
Min.
Unit
Symbol
Switching characteristics (VCC = 5 V ± 10 %, VSS = 0 V, Ta = 0 to 70 °C, f(XIN) = 20 MHz, unless otherwise noted)
0.5tc + 10
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