Corrections and Supplementary Explanation for M37906MxX Datasheet (Rev.C) No.5
(5/7)
Page
Error
Correction
Page 75,
Left column
Line 20
selects the PLL circuit’s operation (stopped/active).
selects the PLL circuit’s operation (inactive/active).
Page 75,
Right column
Lines 1, 7, 12
the frequency of the PLL output clock (fPLL)
the frequency of fPLL
Page 75,
Right column
Line 11
, and fXIN is select as the system clock when bit 5 = “0”.
, and input clock fXIN is select as the system clock
when bit 5 = “0”.
Page 75,
Right column
Line 22
, and these bits select the multiplication ratio of (f1 to
f4096)/(fsys).
, and these bits select the division ratio of (f1 to
f4096)/(fsys).
Page 75,
Table 9
Note
Note: The PLL multiplication must be set so that the fre-
quency of the PLL output clock (fPLL) must be
Note: The PLL multiplication must be set so that the fre-
quency of fPLL must be
Page 76,
Fig. 84
PLL frequency
multiplier
fPLL
System clock
frequency select bit
PLL frequency
multiplier
fPLL
System clock
select bit
Page 77,
Fig. 86
Particular function select register 0
10
2
43
5
External clock input select bit (Note)
0: Oscillation circuit is active. (Oscillator
is connected.)
1: Oscillation circuit is inactive. (External
clock is input.)
0
Particular function select register 0
10
2
43
5
External clock input select bit (Note)
0: Oscillation circuit is active. (The osci-
llator is connected.)
1: Oscillation circuit is inactive. (The
externally-generated clock is input.)
0
Page 78,
Left column
Lines 4, 5
These modes are used to save the power dissipation of
the system, by stopping oscillation or system clock in the
case that the CPU needs not be operating.
These modes are used to save the power dissipation of
the system, by making oscillation or system clock inactive
in the case that the CPU needs not be active.
Page 78,
Left column
Line 12
The interrupt priority level of this interrupt is required to
be higher than the
The interrupt priority level of this interrupt needs to be
higher than the
Page 78,
Right column
Lines 2, 3
The execution of the STP instruction stops the oscillation
circuit and PLL circuit. It also stops input clock fXIN,
system clock fsys,
The execution of the STP instruction makes the oscillation
circuit and PLL circuit inactive. It also makes the following
inactive: input clock fXIN, system clock fsys,
Page 78,
Left column
After line 29
Table 11 explains the microcomputer’s operation in the
STP and WIT modes.
The external bus fixation function can also be provided.
This function enables the user to specify the states of the
external bus and the bus control signals in the memory
expansion and the microprocessor mode in the STP or
WIT mode. For more information, refer to the section on
the power saving function.
Table 11 explains the microcomputer’s operation in the
STP and WIT modes.
Page 78,
Right column
Line 13
At this time, timers A and B operate only in the event
counter mode,
At this time, timers A and B can be active only in the
event counter mode,
(In this case, the PLL circuit is active.)
(In this case, the PLL circuit operates.)
Page 75,
Left column
Line 25
Page 75,
Left column
Line 23
At the STP instruction execution, the PLL circuit stops its
operation, and
At the STP instruction execution, the PLL circuit is active,
and
Page 78,
Right column
Lines 5, 6
, Wf32, and Wf512 in the “L” state, and divide clocks fX 16
to fX128 in the “H” state.
, Wf32, and Wf512 with the “L” state, and divide clocks
fX16 to fX128 with the “H” state.