參數資料
型號: M37906M6C-XXXFP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PDSO42
封裝: 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-42
文件頁數: 13/104頁
文件大小: 995K
代理商: M37906M6C-XXXFP
13
M37906M4C-XXXFP, M37906M4C-XXXSP, M37906M4H-XXXFP
M37906M4H-XXXSP, M37906M6C-XXXFP, M37906M6C-XXXSP
M37906M8C-XXXFP, M37906M8C-XXXSP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Som
e param
etric
lim
its are
subject
to change.
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
5. Index register length flag (x)
The index register length flag determines whether index register X
and index register Y are used as 16-bit registers or as 8-bit registers.
The registers are used as 16-bit registers when flag x is “0” and as 8-
bit registers when it is “1”.
This flag can be set and reset with the SEP and CLP instructions.
6. Data length flag (m)
The data length flag determines whether the data length is 16-bit or
8-bit. The data length is 16 bits when flag m is “0” and 8 bits when it
is “1”. This flag can be set and reset with the SEM and CLM instruc-
tions or with the SEP and CLP instructions.
7. Overflow flag (V)
The overflow flag is valid when addition or subtraction is performed
with a word treated as a signed binary number. If data length flag m
is “0”, the overflow flag is set when the result of addition or subtrac-
tion is outside the range between –32768 and +32767. If data length
flag m is “1”, the overflow flag is set when the result of addition or
subtraction is outside the range between –128 and +127. It is reset
in all other cases. The overflow flag can also be set and reset directly
with the SEP, and CLV or CLP instructions.
Additionally, the overflow flag is set when a result of unsigned/signed
division exceeds the length of the register where the result is to be
stored; the flag is also set when the addition result is outside range
of –2147483648 to +2147483647 in the RMPA operation.
8. Negative flag (N)
The negative flag is set when the result of arithmetic operation or
data transfer is negative (If data length flag m is “0”, data’s bit 15 is
“1”. If data length flag m is “1”, data’s bit 7 is “1”.) It is reset in all other
cases. It can also be set and reset with the SEP and CLP instruc-
tions.
9. Processor interrupt priority level (IPL)
The processor interrupt priority level (IPL) consists of 3 bits and de-
termines the priority of processor interrupts from level 0 to level 7.
Interrupt is enabled when the interrupt priority of the device request-
ing interrupt (set using the interrupt control register) is higher than
the processor interrupt priority. When an interrupt is enabled, the cur-
rent processor interrupt priority level is saved in a stack and the pro-
cessor interrupt priority level is replaced by the interrupt priority level
of the device requesting the interrupt. Refer to the section on inter-
rupts for more details.
Note: Fix bits 11 to 15 of the processor status register (PS) to “0”.
相關PDF資料
PDF描述
M37906M8C-XXXFP 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PDSO42
M37906M4H-XXXSP 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PDIP42
M37906M4C-XXXFP 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PDSO42
M37906M8C-XXXFP 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PDSO42
M37906M6C-XXXSP 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PDIP42
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