參數(shù)資料
型號(hào)： M37906M4C-XXXFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PDSO42
封裝： 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-42
文件頁(yè)數(shù)： 16/99頁(yè)
文件大小： 1313K
代理商： M37906M4C-XXXFP
45
8168C-MCU Wireless-02/10
AT86RF212
RX_AACK configuration steps:
Setup Frame Filter:
registers 0x20 – 0x2B
o
Short address, PAN ID, and IEEE address
Configure acknowledgement generation
registers 0x2C, 0x2E
o
Handling of Frame Version Subfield
o
Handling of Pending Data
o
Automatic or slotted ACK generation
Additional Frame Filtering Properties
register 0x17
o
Frame Filter Version Control
o
Characterize the device as PAN coordinator if required
o
Promiscuous Mode
o
Handling of reserved frame types
The configuration of the Frame Filter is described in section 6.2.1. The addresses for
the address match algorithm are to be stored in the appropriate address registers.
Additional control of the RX_AACK mode is done with register 0x17 (XAH_CTRL_1)
and register 0x2E (CSMA_SEED_1).
Configuration examples for different device operating modes and handling of various
frame types can be found in section 5.2.3.1.
TX_ARET configuration steps:
Enable automatic FCS handling if necessary
register 0x04
Configure CSMA-CA
o
MAX_FRAME_RETRIES
register 0x2C
o
MAX_CSMA_RETRIES
register 0x2C
o
CSMA_SEED
registers 0x2D, 0x2E
o
MAX_BE, MIN_BE
register 0x2F
Configure CCA (see section 6.6)
MAX_FRAME_RETRIES (register 0x2C, XAH_CTRL_0) defines the maximum number
of frame retransmissions.
The register bits MAX_CSMA_RETRIES (register 0x2C) configure the maximum
number of CSMA-CA retries after a busy channel is detected.
The CSMA_SEED_0 and CSMA_SEED_1 register bits (registers 0x2D and 0x2E)
define a random seed for the backoff time random-number generator in the
AT86RF212.
The register bits MAX_BE and MIN_BE (register 0x2F) define the maximum and
minimum CSMA backoff exponent, respectively.
5.2.3 RX_AACK_ON – Receive with Automatic ACK
The RX_AACK Extended Operating Mode handles reception and automatic
acknowledgement of IEEE 802.15.4 compliant frames.
The general flow of the RX_AACK algorithm is shown in Figure 5-9. Here the gray
shaded area is the standard flow of an RX_AACK transaction for IEEE 802.15.4
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