CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual
3-15
3.2 Chip select wait controller
s Area CSj bus cycle select bit 0 (bits 0, 1)
The combination of this bit and the area CSj bus cycle select bit 1 (bit 3 at addresses 8316, 8516,
8716) selects the bus cycle at access to area CSj. (Refer to section “3.2.2 External bus operations.”)
s External data bus width select bit (bit 2)
When the input level at pin BYTE = Vss level, this bit can arbitrarily select the external data bus
width at access to area CSj.
When the input level at pin BYTE = Vcc level, the external data bus width = 8 bits regardless of
this bit’s contents.
s RDY control bit (bit 3)
This bit decides whether the RDY control is valid or not at access to area CSj.
While the RDY input select bit (bit 2 at address 5F16) = “1,” this bit is valid. (Refer to section “3.3
Ready function.”)
s Burst ROM access select bit (bit 5)
When ROM, etc., supporting burst access, is allocated to area CSj, the burst access for the
maximum of 8 bytes becomes available if this bit is set to “1.” The burst ROM access is valid only
when the external data bus width = 16 bits with instructions prefetched. When the external data
bus width = 8 bits or when data is read or written, “normal access” is specified regardless of this
bit’s contents. (Refer to section “3.2.2 External bus operations.”)
s Recovery cycle insert select bit (bit 6)
This bit decides whether recovery cycles are inserted or not at access to area CSj. Setting this bit
to “1” inserts such recovery cycles as 1 or 2 cycles of
φ1 after the bus cycle for accessing area
CSj. The number of recovery cycles to be inserted is selected by the recovery-cycle-insert number
select bit (bit 6 at address 5F16). Insertion of recovery cycles allows devices with longer output
disable time at read to be connected without using bus buffers.
Since addresses are maintained throughout recovery cycles, devices requiring longer address hold
time can easily be connected; on the other hand, by inserting 2 recovery cycles to extend the data
hold time at write by 1 cycle of
φ1, devices requiring longer data hold time can also be connected.
(Refer to section “3.2.2 External bus operations.”)
s CSj output select bit (bit 7)
Setting this bit to “1” outputs a chip select signal at access to area CSj.
Even though clearing this bit to “0” in order to disable CSj output, setting for each function of area
CSj (See Table 3.2.1.) is valid if the area CSj block size select bits (bits 2 to 0 at addresses 8316,
8516, 8716) are not “0002” (in other words, area CSj is invalid.)
Moreover, even when area CSj is invalid, setting this bit to “1” validates pin CSj. (“H” level is
output.)