FLASH MEMORY VERSION
7902 Group User’s Manual
20-14
20.2 Flash memory CPU reprogramming mode
20.2.1 Flash memory control register
Figure 20.2.1 shows the structure of the flash memory control register.
0
1
2
3
4
5
7, 6
RY/BY status bit
CPU reprogramming mode select bit
Lock bit invalidity select bit
Flash memory reset bit (Note 5)
Fix this bit to “0.”
User ROM area select bit
(Valid in boot mode)
(Note 7)
The value is “0” at reading.
RO
RW
(Notes 1, 2)
RW
(Notes 1, 4)
RW
(Note 6)
RW
(Note 2)
—
1
0
0 : Lock bit is valid.
1 : Lock bit is invalid (Note 3).
Bit name
Bit
Flash memory control register (Address 9E16)
Function
At reset
R/W
b7 b6 b5 b4 b3 b2 b1 b0
0 : BUSY (Automatic programming or erase operation
is active.)
1 : READY (Automatic programming or erase operation
has been completed.)
0 : Flash memory CPU reprogramming mode is invalid.
1 : Flash memory CPU reprogramming mode is valid.
Notes 1: In order to set this bit to “1,” write “0” followed with “1” successively; while in order to clear this bit “0,” write “0.”
2: Writing to this bit must be performed in an area other than the internal flash memory.
3: Simultaneously with the CPU reprogramming mode select bit (bit 1) cleared “0,” this bit is also cleared to “0.”
4: Only when the CPU reprogramming mode select bit (bit 1) = “1,” writing to this bit is available.
5: This bit is valid only when the CPU reprogramming mode select bit = “1”: on the other hand, when the CPU reprogra-
mming mode select bit = “0,” be sure to fix this bit to “0.”
6: After writing of “1” to this bit, be sure to write “0” successively.
7: When MD1 = Vss level, this bit is invalid. (It may be either “0” or “1.”)
0 : Access to boot ROM area
1 : Access to user ROM area
Writing “1” followed with “0” into this bit discontinues
the access to the internal flash memory. This causes
the built-in flash memory circuit being reset.
0
(1) RY/BY status bit (bit 0)
This bit is used to indicate the operating status of the write state machine (hereafter referred to WSM)
as well as the WSM status bit (SR.7 of the status register; refer to section “20.2.2 Status register.”).
This bit is “0” during the automatic programming or erase operation is active and becomes “1” upon
completion of them. This bit also changes during the execution of the page programming, block erase,
erase all unlocked block, or the lock bit programming command, but does not change owing to the
execution of another command.
(2) CPU reprogramming mode select bit (bit 1)
Setting this bit to “1” allows the microcomputer to enter the flash memory CPU reprogramming mode
to accept commands. In order to set this bit to “1,” write “1” followed with “0” successively; while to
clear this bit to “0,” write “0.”
Since the microcomputer enters the flash memory CPU reprogramming mode after setting this bit to
“1,” opcodes cannot be fetched for the internal flash memory. Accordingly, be sure to execute the
instruction to be used for writing to this bit in an area other than the internal flash memory area (e.g.
the internal RAM area).
When executing commands of the flash memory CPU reprogramming mode in the boot mode, be sure
to set the user ROM area select bit (bit 5) to “1.”
Fig. 20.2.1 Structure of flash memory control register