D-A CONVERTER
7902 Group User’s Manual
14-4
14.2.3 A-D control register 1
Figure 14.2.4 shows the structure of the A-D control register 1.
Fig.14.2.4 Structure of A-D control register 1
(1) VREF connection select bit (Bit 6)
This bit is used to disconnect the ladder network of the D-A converters from the reference voltage
input pin (VREF) when A-D and D-A converters are not used.
Disconnecting the ladder network from pin VREF prevents the current flow from pin VREF to the network
to save the current consumption.
When this bit is cleared from “1” (VREF disconnected) to “0” (VREF connected), start D-A conversion after
1 s or more has elapsed.
14.2 Block description
0
1
2
3
4
5
6
7
Notes 1: These bits are invalid in the one-shot and repeat modes. (They may be either “0” or “1.”)
2: When using pin AN4, be sure that the pin INT3 select bit (bit 5 at address 9416) = “0.”
3: When using pin AN5, be sure that the pin INT4 select bit (bit 6 at address 9416) = “0.”
4: When using pin AN6, be sure that the D-A0 output enable bit (bit 0 at address 9616) = “0” (output disabled).
5: When using pin AN7, be sure that the pin INT2 select bit (bit 4 at address 9416) = “0” and the D-A1 output enable bit (bit 1
at address 9616) = “0.” When an external trigger is selected, pin AN7 cannot be used as an analog input pin.
6: When this bit is cleared from “1” to “0,” be sure to start the A-D conversion or D-A conversion after an interval of 1 s or
more has elapsed.
7: Writing to each bit of the A-D control register 1 must be performed while the A-D conversion halts.
1
0
RW
—
Bit name
Bit
A-D control register 1 (Address 1F16 )
Function
At reset
R/W
A-D sweep pin select bits
(Valid in the single sweep and repeat
sweep modes.)
(Note 1)
Fix this bit to “0.”
Resolution select bit
A-D convertion frequency (
φAD) select bit 1
External trigger polarity select bit
(Valid when external trigger is selected.)
VREF connection select bit (Note 6)
The value is “0” at reading.
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Pins AN0 and AN1 (2 pins)
0 1 : Pins AN0 to AN3 (4 pins)
1 0 : Pins AN0 to AN5 (6 pins) (Notes 2, 3)
1 1 : Pins AN0 to AN7 (8 pins) (Notes 2 to 5)
b1 b0
0 : 8-bit resolution mode
1 : 10-bit resolution mode
See Table 13.2.1.
0
0 : Falling edge of the pin ADTRG’s input signal
1 : Rising edge of the pin ADTRG’s input signal
0 : Pin VREF is connected.
1 : Pin VREF is not connected.