- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45037 > M37754S4CHP 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100 PDF資料下載
參數(shù)資料
| 型號： | M37754S4CHP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 0.50 MM PITCH, FINE PITCH, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 50/114頁 |
| 文件大?。?/td> | 1116K |
| 代理商： | M37754S4CHP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁當(dāng)前第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁
40
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Three-phase mode 1
In selecting three-phase waveform mode, three-phase mode 1 is
selected by setting bit 4 of the waveform output mode register (ad-
dress 1A16) to “1”.
In this mode, each of timers A0 to A2 can have two timer registers
and the contents of those registers are alternately reloaded into the
counter each time the counter of timer B2 becomes 000016. About
write operation to two timer registers, when rewriting to each timer
register of timers A0, A1 and A2 after writing to each timer register of
them, the data is written each to timers A01, A11 and A21. When writ-
ing to each timer register, the timer A write register (in Figure 46) in-
dicates the timer to be intended for write.
The interrupt request normally occurs when the counter of timer B2
becomes 000016. However, this occurrence interval can be switched
between “every second time” and “every fourth time.” Bit 0 of the
pulse output data register 1 (address 1C16) selects that.
Additionally, “0” or “1” of the three-phase output polarity set buffer
can be used as the occurrence factor of timer B2 interrupt request.
Bit 1 of the pulse output data register 1 (address 1C16) selects that.
When the timer B2’s counter contents become 000016, the contents
of three-phase output polarity set buffer are set into the output polar-
ity set toggle flip-flop on which .the output polarity of three-phase
waveform depends. The contents of three-phase output polarity set
buffer are reversed after that operation.
The polarity of the contents of output polarity set toggle flip-flop is re-
versed each time completion of one-shot pulse of timer (timers A2 to
A0) corresponding to each phase.
Figure 47 shows an example of U-phase waveform and the output
operation is explained.
Write “0” to the three-phase output polarity set buffer (bit 3 at ad-
dress 1A16). Clear the interrupt request interval set bit (bit 0 at ad-
dress 1C16) to “0” so that the timer B2 interrupt request may occur at
every second time. Additionally, clear the interrupt validity output se-
lect bit (bit 1 at address 1C16) so that the timer B2 interrupt request
may occur at “0” of the three-phase output polarity set buffer.
After the procedure above, three-phase mode 1 starts operation
when actuating the timer B2.
When the counter of timer B2 becomes 000016, the timer B2 inter-
rupt request occurs and timer A2 simultaneously starts one-shot
pulse output. At this time, the contents of three-phase output polarity
set buffer, “0” in this case, are set into the output polarity set toggle
flip-flop 2. The contents of three-phase output polarity set buffer are
reversed from “0” to “1” after that operation.
When the timer A2 counter counts the value written into the timer A2
and the one-shot pulse output of timer A2 is completed, the contents
of output polarity set toggle flip-flop 2 are reversed from “0” to “1”. Si-
multaneously, the one-shot pulse of the 8-bit dead-time timer is out-
__
put for ensuring time, so that “L” levels of U- and U-phase waveforms
do not overlap.
Timer B2 interrupt request
signal
Signal output each time
Timer B2 becomes 000016
One-shot pulse output with
timer A2
Timer A2
Timer A21
Contents of output polarity
set toggle flip-flop 2
Reversed
pulse
output
signal with dead-time timer
U-phase waveform output
n1
n3
n5
n7
n2
n4
n6
n8
n2
n3
n4
n5
n6
Address
Timer A write register 4516
Timer A0 write bit
0 : Write to timer A0
1 : Write to timer A01
Timer A1 write bit
0 : Write to timer A1
1 : Write to timer A11
Timer A2 write bit
0 : Write to timer A2
1 : Write to timer A21
76543210
Note : Only when bit 5 of the particular function select register 1 (in Fig. 15)
is set to “1”, this register’s contents can be changed from the status
after reset (in Fig.76).
Fig. 47 U-phase waveform output example in three-phase mode 1 (triangular wave modulation)
Fig. 46 Timer A write flag bit configuration
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M37754S4CHP | 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100 |
| M37754M8C-XXXGP | 16-BIT, MROM, 40 MHz, MICROCONTROLLER, PQFP100 |
| M37777E9AGS | 16-BIT, UVPROM, 16 MHz, MICROCONTROLLER, CQCC100 |
| M34550M6A-XXXFP | 4-BIT, MROM, 1.6 MHz, MICROCONTROLLER, PQFP80 |
| M37776M5AXXXGP | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M3775PR-H400CL | 制造商:Bonitron 功能描述:OVERVOLTAGE BRAKING RESISTOR |
| M3775RK-0.75A | 制造商:Bonitron 功能描述:OVERVOLTAGE BRAKING RESISTOR |
| M3775RK-C0.50A | 制造商:Bonitron 功能描述:OVERVOLTAGE BRAKING RESISTOR |
| M3775RK-C0.50B | 制造商:Bonitron 功能描述:OVERVOLTAGE BRAKING RESISTOR |
| M3775RK-C0.50C | 制造商:Bonitron 功能描述:OVERVOLTAGE BRAKING RESISTOR |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。