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參數(shù)資料
| 型號(hào)： | M37754S4CHP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 0.50 MM PITCH, FINE PITCH, PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 26/114頁(yè) |
| 文件大?。?/td> | 1116K |
| 代理商： | M37754S4CHP |
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19
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 3. Addresses of interrupt control registers
Interrupt control registers
INT4 interrupt control register
INT3 interrupt control register
A-D interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT0 interrupt control register
INT1 interrupt control register
____
INT2 interrupt control register
Addresses
00006E16
00006F16
00007016
00007116
00007216
00007316
00007416
00007516
00007616
00007716
00007816
00007916
00007A16
00007B16
00007C16
00007D16
00007E16
00007F16
The interrupt request bit and the interrupt priority level of each inter-
rupt source are sampled and latched at each operation code fetch
cycle while
φBIU is “H”. However, no sampling pulse is generated
until the cycles whose number is selected by software has passed,
even if the next operation code fetch cycle is generated. The detec-
tion of an interrupt which has the highest priority is performed during
that time.
Fig. 11 Interrupt priority
Fig. 12 Interrupt priority detection
Interrupts caused by a BRK instruction and when dividing by zero are
software interrupts and are not included in this list.
Other interrupts previously mentioned are A-D converter, UART, etc.
interrupts. The priority of these interrupts can be changed by chang-
ing the priority level in the corresponding interrupt control register by
software.
Figure 12 shows a diagram of the interrupt priority detection circuit
When an interrupt is caused, each interrupt device compares its own
priority with the priority from above and if its own priority is higher,
then it sends the priority below and requests the interrupt. If the pri-
orities are the same, the one above has priority.
This comparison is repeated to select the interrupt with the highest
priority among the interrupts that are being requested. Finally the
selected interrupt is compared with the processor interrupt priority
level (IPL) contained in the processor status register (PS) and the
request is accepted if it is higher than IPL and the interrupt disable
___
flag I is “0”. The request is not accepted if flag I is “1”. The reset, DBC,
and watchdog timer interrupts are not affected by the interrupt dis-
able flag I.
When an interrupt is accepted, the contents of the processor status
register (PS) is saved to the stack and the interrupt disable flag I is
set to “1”.
Furthermore, the interrupt request bit of the accepted interrupt is
cleared to “0” and the processor interrupt priority level (IPL) in the
processor status register (PS) is replaced by the priority level of the
accepted interrupt.
Therefore, multi-level priority interrupts are possible by resetting the
interrupt disable flag I to “0” and enable further interrupts.
___
For reset, DBC, watchdog timer, zero divide, and BRK instruction in-
terrupts, which do not have an interrupt control register, the proces-
sor interrupt level (IPL) is set as shown in Table 4.
Watchdog
timer
DBC
Priority is determined by hardware
A-D converter, UART, etc. interrupts
Priority can be changed with software inside 4
Reset
4
321
Reset
A-D
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
INT2
DBC
Watchdog timer
IPL
Interrupt request
Level 0
Interrupt disable flag I
INT3
INT1
INT2
INT1
INT0
INT4
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