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CONNECTION WITH EXTERNAL DEVICES
7721 Group User’s Manual
3–3
3.1 Signals required for accessing external devices
Fig. 3.1.1 Pin configurations when external data bus width is 16 bits and 8 bits (top view)
P8
7
/T
X
D
1
P9
0
/DMAACK0
P9
1
/DMAREQ0
P9
2
/DMAACK1
P9
3
/DMAREQ1
P9
4
/DMAACK2
P9
5
/DMAREQ2
P9
6
/DMAACK3
P9
7
/DMAREQ3
A
0
/MA
0
A
1
/MA
1
A
2
/MA
2
A
3
/MA
3
A
4
/MA
4
A
5
/MA
5
A
6
/MA
6
A
7
/MA
7
A
8
/D
8
A
9
/D
9
A
10
/D
10
A
11
/D
11
A
12
/D
12
A
13
/D
13
A
14
/D
14
A
15
/D
15
A
16
/D
0
A
17
/D
1
A
18
/D
2
A
19
/D
3
A
20
/D
4
P86/RXD1
P85/CLK1
P84/CTS1/RTS1
P83/TXD0
P82/RXD0
P81/CLK0
P80/CTS0/RTS0
VCC
AVCC
VREF
AVSS
VSS
P77/AN7/ADTRG
P76/AN6
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
P70/AN0
P6
7
/RTP1
3
P6
6
/RTP1
2
P6
5
/RTP1
1
P6
4
/RTP1
0
P6
3
/RTP0
3
P6
2
/RTP0
2
P6
1
/RTP0
1
P6
0
/RTP0
0
P5
7
/TB1
IN
P5
6
/TB0
IN
P5
5
/TA4
IN
P5
4
/TA4
OUT
P5
3
/TA3
IN
P5
2
/TA3
OUT
P5
1
/TA2
IN
P5
0
/TA2
OUT
P10
7
/MA
9
P10
6
/MA
8
P10
5
/RAS
P10
4
/CAS
P10
3
/TC
P10
2
/INT
2
P10
1
/INT
1
P10
0
/INT
0
P4
7
P4
6
P4
5
P4
4
P4
3
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
4
3
2
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A21/D5
A22/D6
A23/D7
R/W
BHE
BLE
ALE
ST0
ST1
VCC
VSS
E
XOUT
XIN
RESET
RESETOUT
CNVSS
BYTE
HOLD
RDY
35
37
36
38
44
39
40
41
42
43
45
46
47
48
49
50
31
32
33
34
96
94
95
93
87
92
91
90
89
88
86
85
84
83
82
81
100
99
98
97
M37721S2BFP
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
35
37
36
38
44
39
40
41
42
43
45
46
47
48
49
50
31
32
33
34
96
94
95
93
87
92
91
90
89
88
86
85
84
83
82
81
100
99
98
97
1
4
3
2
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P86/RXD1
P85/CLK1
P84/CTS1/RTS1
P83/TXD0
P82/RXD0
P81/CLK0
P80/CTS0/RTS0
VCC
AVCC
VREF
AVSS
VSS
P77/AN7/ADTRG
P76/AN6
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
P70/AN0
P6
7
/RTP1
3
P6
6
/RTP1
2
P6
5
/RTP1
1
P6
4
/RTP1
0
P6
3
/RTP0
3
P6
2
/RTP0
2
P6
1
/RTP0
1
P6
0
/RTP0
0
P5
7
/TB1
IN
P5
6
/TB0
IN
P5
5
/TA4
IN
P5
4
/TA4
OUT
P5
3
/TA3
IN
P5
2
/TA3
OUT
P5
1
/TA2
IN
P5
0
/TA2
OUT
P10
7
/MA
9
P10
6
/MA
8
P10
5
/RAS
P10
4
/CAS
P10
3
/TC
P10
2
/INT
2
P10
1
/INT
1
P10
0
/INT
0
P4
7
P4
6
P4
5
P4
4
P4
3
1
A21/D5
A22/D6
A23/D7
R/W
BHE
BLE
ALE
ST0
ST1
VCC
VSS
E
XOUT
XIN
RESET
RESETOUT
CNVSS
BYTE
HOLD
RDY
M37721S2BFP
qExternal data bus width = 16 bits (BYTE = “L”)
: External address bus, external data bus,
bus control signal
qExternal data bus width = 8 bits (BYTE = “H”)
Note: For the DRAM control signals, refer to “CHAPTER 14. DRAM CONTROLLER.”
: External address bus, external data bus,
bus control signal
P8
7
/T
X
D
1
P9
0
/DMAACK0
P9
1
/DMAREQ0
P9
2
/DMAACK1
P9
3
/DMAREQ1
P9
4
/DMAACK2
P9
5
/DMAREQ2
P9
6
/DMAACK3
P9
7
/DMAREQ3
A
0
/MA
0
A
1
/MA
1
A
2
/MA
2
A
3
/MA
3
A
4
/MA
4
A
5
/MA
5
A
6
/MA
6
A
7
/MA
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
/D
0
A
17
/D
1
A
18
/D
2
A
19
/D
3
A
20
/D
4