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SERIAL I/O
7721 Group User’s Manual
11–6
11.2 Block description
11.2.2 UARTi transmit/receive control register 0
Figure 11.2.3 shows the structure of UARTi transmit/receive control register 0. For bits 0 and 1, refer to
section “11.2.1 (1) Internal/External clock select bit (bit 3).”
Fig. 11.2.3 Structure of UARTi transmit/receive control register 0
(1)
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CTS/RTS select bit (bit 2)
____
By clearing this bit to “0” in order to select the CTS function, pins P80 and P84 function as CTS input
pins, and the input signal of “L” level to these pins becomes one of the transmission conditions.
____
By setting this bit to “1” in order to select the RTS function, pins P80 and P84 become RTS output
____
pins. When the receive enable bit (bit 2 at addresses 3516, 3D16) is “0” (reception disabled), the RTS
output pin outputs “H” level.
____
In the clock synchronous serial I/O mode, the output level of the RTS pin becomes “L” when reception
conditions are satisfied, and it becomes “H” when reception starts. Note that, when an internal clock
____
is selected (bit 3 at addresses 3016, 3816 = “0”), the RTS output is undefined. Accordingly, do not
____
select the RTS function.
____
In the clock asynchronous serial I/O mode, the output level of the RTS pin becomes “L” when the
receive enable bit is set to “1.” It becomes “H” when reception starts and it becomes “L” when
reception is completed.
(2)
Transmit register empty flag (bit 3)
This flag is cleared to “0” when the UARTi transmit buffer register’s contents are transferred to the
UARTi transmit register. When transmission is completed and the UARTi transmit register becomes
empty, this flag is set to “1.”
CTS/RTS select bit
Bit
1
BRG count source select bits
Bit name
At reset
RW
Functions
b7
b6
b5
b4
b3
b2
b1
b0
0 0 : f2
0 1 : f16
1 0 : f64
1 1 : f512
UART0 transmit/receive control register 0 (Address 3416)
UART1 transmit/receive control register 0 (Address 3C16)
b1 b0
0 : CTS function selected
1 : RTS function selected
Transmit register empty flag
0 : Data present in transmit register
(During transmission)
1 : No data present in transmit register
(Transmission completed)
1
0
2
RW
RO
3
RW
7 to 4
Nothing is assigned.
Undefined
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