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參數(shù)資料
| 型號(hào)： | M37643F8HP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件頁(yè)數(shù)： | 40/120頁(yè) |
| 文件大?。?/td> | 1253K |
| 代理商： | M37643F8HP |
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26
7643 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to
change.
SERIAL I/O
The serial I/O can be used only for clock synchronous serial I/O.
The transmitter and the receiver must use the same clock. If the
internal clock is used, transfer is started by a write signal to the
serial I/O shift register.
[Serial I/O Control Register 1 (SIOCON1)] 002B16
[Serial I/O Control Register 2 (SIOCON2)] 002C16
Each of the serial I/O control registers 1 and 2 contains eight bits
which control various serial I/O functions.
Fig. 21 Structure of serial I/O control registers 1, 2
Serial I/O control register 1 (address 002B16)
SIOCON1
Internal synchronous clock select bits (Note 1)
b2b1b0
0 0 0: Internal clock divided by 2
0 0 1: Internal clock divided by 4
0 1 0: Internal clock divided by 8
0 1 1: Internal clock divided by 16
1 0 0: Internal clock divided by 32
1 0 1: Internal clock divided by 64
1 1 0: Internal clock divided by 128
1 1 1: Internal clock divided by 256
Serial I/O port select bit
0: I/O port
1: STXD, SCLK signal output
SRDY output select bit
0: I/O port
1: SRDY signal output
Transfer direction select bit
0: LSB first
1: MSB first
Synchronous clock select bit
0: External clock
1: Internal clock
STXD output channel control bit
0: CMOS output
1: N-channel open drain output
Notes 1: The source of serial I/O internal synchronous clock can be selected by bit 1
of serial I/O control register 2.
2: To set the slave mode, also set bit 4 of serial I/O control register 1 to “1”.
b0
b7
Serial I/O control register 2 (address 002C16)
SIOCON2
SPI mode select bit
0: Normal serial I/O mode
1: SPI compatible mode (
Note 2)
Reserved bit (“0” at read/write)
SRXD input enable bit
0: SRXD input disabed
1: SRXD input enabed
Clock polarity select bit (CPoL)
0: SCLK starting at “L”
1: SCLK starting at “H”
Clock phase select bit (CPha)
0: Serial transfer starting at falling edge of SRDY
1: Serial transfer starting afer a half cycle of SCLK
passed at falling edge of SRDY
Reserved bits (“0” at read/write)
b0
b7
000
0
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| M37643F8M8-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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