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Rev.2.00
Aug 28, 2006
page 12 of 13
7641 Group
REJ09B0336-0200
List of tables
CHAPTER 1 HARDWARE
Table 1 Pin description (1) .............................................................................................................. 5
Table 2 Pin description (2) .............................................................................................................. 6
Table 3 Support products ................................................................................................................ 8
Table 4 Push and pop instructions of accumulator or processor status register .................. 10
Table 5 Set and clear instructions of each bit of processor status register .......................... 11
Table 6 List of I/O port function ................................................................................................... 16
Table 7 Interrupt vector addresses and priority ......................................................................... 22
Table 8 Function description of control I/O pins of master CPU bus interface ..................... 64
Table 9 Port functions in memory expansion mode and microprocessor mode ......... 75
Table 10 Summary of M37641F8 (flash memory version) ........................................................ 81
Table 11 List of software commands (CPU rewrite mode) ....................................................... 86
Table 12 Definition of each bit in status register (SRD) ........................................................... 88
Table 13 Description of pin function (Standard Serial I/O Mode) ............................................ 94
Table 14 Software commands (Standard serial I/O mode) ....................................................... 97
Table 15 Definition of each bit of status register (SRD) ........................................................ 104
Table 16 Definition of each bit of status register 1 (SRD1) ................................................... 105
Table 17 Bits of which state might be changed owing to software write ............................. 109
CHAPTER 2 APPLICATION
Table 2.1.1 Termination of unused pins ........................................................................................ 9
Table 2.4.1 Setting examples of baud rate generator values and transfer bit rate values
(
φ = 12 MHz)) ............................................................................................................. 61
Table 2.4.2 Setting examples of SCSG1, SCSG2 and baud rate generator values and transfer
bit rate values (
φ = 12 MHz)) .................................................................................. 63
Table 2.4.3 Error flags set condition and how to clear error flags ......................................... 65
Table 2.5.1 Address directions and examples of transfer result (1) ....................................... 90
Table 2.5.2 Address directions and examples of transfer result (2) ....................................... 91
Table 2.5.3 Priority to use bus ..................................................................................................... 92
Table 2.8.1 Bus control signal and data bus state-RD/WR separate type ........................... 111
Table 2.8.2 Bus control signal and data bus state-R/W type ................................................ 111
Table 2.12.1 State in Stop mode ................................................................................................ 139
Table 2.12.2 State in Wait mode ................................................................................................ 140
CHAPTER 3 APPENDIX
Table 3.1.1 Absolute maximum ratings ........................................................................................ 2
Table 3.1.2 Recommended operating conditions (Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = –20
to 70°C, unless otherwise noted) ............................................................................. 3
Table 3.1.3 Electrical characteristics (1) (Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = –20 to 70°C,
unless otherwise noted) ............................................................................................. 4
Table 3.1.4 Electrical characteristics (2) (Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = –20 to 70°C,
unless otherwise noted) ............................................................................................. 5
Table 3.1.5 Timing requirements (Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = –20 to 70°C, unless
otherwise noted) .......................................................................................................... 6
Table 3.1.6 Master CPU bus interface (MBI; RD, WR separate type) (Vcc = 4.15 to 5.25 V,
Vss = 0 V, Ta = –20 to 70°C, unless otherwise noted) ....................................... 7
List of tables