![](http://datasheet.mmic.net.cn/90000/M37641M8-XXXHP_datasheet_3496247/M37641M8-XXXHP_6.png)
Rev.2.00
Aug 28, 2006
page 2 of 13
7641 Group
REJ09B0336-0200
2.3 Serial I/O ................................................................................................................................... 38
2.3.1 Memory map .................................................................................................................... 38
2.3.2 Related registers ............................................................................................................. 39
2.3.3 Serial I/O connection examples .................................................................................... 42
2.3.4 Serial I/O application examples .................................................................................... 44
2.3.5 Notes on serial I/O ......................................................................................................... 51
2.4 UART ......................................................................................................................................... 52
2.4.1 Memory map .................................................................................................................... 52
2.4.2 Related registers ............................................................................................................. 53
2.4.3 UART transfer data format ............................................................................................ 60
2.4.4 Transfer bit rate .............................................................................................................. 61
2.4.5 Operation of transmitting and receiving ....................................................................... 64
2.4.6 UART application example ............................................................................................. 66
2.4.7 Notes on UART ............................................................................................................... 77
2.5 DMAC ......................................................................................................................................... 79
2.5.1 Memory map .................................................................................................................... 79
2.5.2 Related registers ............................................................................................................. 80
2.5.3 DMAC operation description .......................................................................................... 88
2.5.4 DMAC arbitration ............................................................................................................. 92
2.5.5 Transfer time .................................................................................................................... 92
2.5.6 DMAC application example ............................................................................................ 95
2.5.7 Notes on DMAC .............................................................................................................. 99
2.6 USB .......................................................................................................................................... 100
2.7 Frequency synthesizer ........................................................................................................ 101
2.7.1 Memory map .................................................................................................................. 101
2.7.2 Related registers ........................................................................................................... 102
2.7.3 Functional description ................................................................................................... 105
2.7.4 Notes on frequency synthesizer .................................................................................. 107
2.8 Master CPU bus interface .................................................................................................. 108
2.8.1 Memory map .................................................................................................................. 108
2.8.2 Related registers ........................................................................................................... 109
2.8.3 Functional description ................................................................................................... 111
2.8.4 Operation description .................................................................................................... 113
2.8.5 Master CPU bus interface application example ........................................................ 114
2.8.6 Notes on master CPU bus interface .......................................................................... 115
2.9 Special count source generator (SCSG) ......................................................................... 116
2.9.1 Memory map .................................................................................................................. 116
2.9.2 Related registers ........................................................................................................... 117
2.9.3 Functional description ................................................................................................... 119
2.10 External devices connection ........................................................................................... 120
2.10.1 Memory map ................................................................................................................ 120
2.10.2 Related registers ......................................................................................................... 121
2.10.3 Functional description ................................................................................................. 122
2.10.4 Slow memory wait ....................................................................................................... 123
2.10.5 HOLD function ............................................................................................................. 126
2.10.6 Expanded data memory access ................................................................................ 127
2.10.7 External devices connection example ...................................................................... 128
2.10.8 Notes on external devices connection ..................................................................... 132
2.11 Reset ..................................................................................................................................... 134
2.11.1 Connection example of reset IC ............................................................................... 134
2.11.2 Notes on reset ............................................................................................................. 134
Table of contents