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Rev.2.00
Aug 28, 2006
page 32 of 108
7641 Group
REJ09B0336-0200
APPENDIX
3.3 Notes on use
3.3.5 Notes on USB
(1) USB reception
When reading the USB endpoint x (x = 0 to 4) OUT write count registers, the lower byte must be
read first, and then the higher byte.
When the OUT FIFO contains 2-data packets in the endpoints 1 to 4 used, one-data packet will still
remain in the OUT FIFO even after the data of the OUT max. packet size has been read. In this
case the OUT_PKT_RDY flag is not cleared even if it is set to “0”. (The flag returns from “0” to “1”
83 ns later (Vcc = 5 V, f(XIN) = 24 MHz) than the clearing.)
Read one packet data from the OUT FIFO before clearing the OUT_PKT_RDY flag. If the OUT_PKT_RDY
flag is cleared while one-data packet is being read, the internal read pointer cannot operate normally.
(2) USB transmission
The IN FIFO status can be checked by monitoring the IN_PKT_RDY bit and the TX_NOT_EPT flag.
When NULL packet transmission is required in the endpoints 1 to 4 used, perform it under the
conditions of the IN_PKT_RDY bit set to “1” and no data in FIFO.
(3) External circuit
Connect a capacitor between the Ext. Cap. pin and the Vss pin. The capacitor should have a 2.2
F capacitor (Tantalum capacitor) and a 0.1 F capacitor (ceramic capacitor) connected in parallel.
Additionally, connect a 1.5 k
(± 5 %) resistor between the Ext. Cap. pin and the D+ pin.
The Full-Speed USB2.0 specification requires a driver -impedance 28 to 44
. (Refer to Clause
7.1.1.1 Full-speed (12 Mb/s) Driver Characteristics in the USB specification.) In order to meet the
USB specification impedance requirements, connect a resistor (27 to 33
recommended) in series
to the USB D+ pin and the USB D- pin.
In addition, in order to reduce the ringing and control the falling/rising timing of USB D+/D- and a
crossover point, connect a capacitor between the USB D+/D- pins and the Vss pin if necessary.
The values and structure of those peripheral elements depend on the impedance characteristics and
the layout of the printed circuit board. Accordingly, evaluate your system and observe waveforms
before actual use and decide use of elements and the values of resistors and capacitors.
Figure 3.3.2 shows the circuit example for the proper positions of the peripheral components.
In Vcc = 3.3 V operation, connect the Ext. Cap. pin directly to the Vcc pin in order to supply power
to the USB transceiver. In addition, you will need to disable the DC-DC converter in this operation
(set bit 4 of the USB control register to “0”.) If you are using the bus powered supply in Vcc = 3.3
V operation, the DC-DC converter must be placed outside the MCU.
In Vcc = 5 V operation, do not connect the external DC-DC converter to the Ext. Cap. pin. Use the
built-in DC-DC converter by enabling the USB line driver.
Make sure the USB D+/D- lines do not cross any other wires. Keep a large GND area to protect the
USB lines. Also, make sure you use a USB specification compliant connecter for the connection.
All passive components must be located as close as possible to the LPF pin. Figure. 3.3.3 shows
the passive components near LPF pin
An insulation connector (Ferrite Beads) must be connected between AVss and Vss pins and between
AVcc and Vcc pins. (See Figure 3.3.4.)
(4) USB Communication
In applications requiring high-reliability, we recommend providing the system with protective measures
such as USB function initialization by software or USB reset by the host to prevent USB communication
from being terminated unexpectedly, for example due to external causes such as noise.