參數(shù)資料
型號(hào)： M37549G1FP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO24
封裝： 5.30 X 10.10 MM, 0.80 MM PITCH, PLASTIC, SSOP-24
文件頁(yè)數(shù)： 4/86頁(yè)
文件大小： 1375K
代理商： M37549G1FP
Rev.2.02
Mar 31, 2009
Page 10 of 81
REJ03B0202-0202
7549 Group
[Processor status register (PS)]
The processor status register is an 8-bit register consisting of flags
which indicate the status of the processor after an arithmetic
operation. Branch operations can be performed by testing the
Carry (C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative
(N) flag. In decimal mode, the Z, V, N flags are not valid.
After reset, the Interrupt disable (I) flag is set to “1”, but all other
flags are undefined. Since the Index X mode (T) and Decimal
mode (D) flags directly affect arithmetic operations, they should
be initialized in the beginning of a program.
Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the
arithmetic logic unit (ALU) immediately after an arithmetic
operation. It can also be changed by a shift or rotate instruction.
Bit 1: Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic
operation or a data transfer is “0”, and cleared if the result is
anything other than “0”.
Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction. Interrupts are disabled
when the I flag is “1”.
When an interrupt occurs, this flag is automatically set to “1”
to prevent other interrupts from interfering until the current
interrupt is serviced.
Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the
ADC and SBC instructions can be used for decimal arithmetic.
Bit 4: Break flag (B)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the
processor status register is always “0”. When the BRK
instruction is used to generate an interrupt, the processor
status register is pushed onto the stack with the break flag set
to “1”. The saved processor status is the only place where the
break flag is ever set.
Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory, e.g. the results of an
operation between two memory locations is stored in the
accumulator. When the T flag is “1”, direct arithmetic
operations and direct data transfers are enabled between
memory locations, i.e. between memory and memory,
memory and I/O, and I/O and I/O. In this case, the result of
an arithmetic operation performed on data in memory
location 1 and memory location 2 is stored in memory
location 1. The address of memory location 1 is specified by
index register X, and the address of memory location 2 is
specified by normal addressing modes.
Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one
byte of signed data. It is set if the result exceeds +127 to -
128. When the BIT instruction is executed, bit 6 of the
memory location operated on by the BIT instruction is stored
in the overflow flag.
Bit 7: Negative flag (N)
The N flag is set if the result of an arithmetic operation or
data transfer is negative. When the BIT instruction is
executed, bit 7 of the memory location operated on by the
BIT instruction is stored in the negative flag.
[CPU mode register] CPUM
The CPU mode register contains the stack page selection bit.
This register is allocated at address 003B16.
Fig 7.
Structure of CPU mode register
The processor mode bits can be written only once after releasing reset.
Always set them to “002”. After written, rewriting any data to these
bits is disabled because they are locked. (Emulator MCU is excluded.)
Also, the stack page selection bit (bit 2) is not locked.
In order to prevent error-writing to the processor mode bits (at
program runaway), write the CPU mode register at the start of
the program that runs after releasing reset.
Table 5
Set and clear instructions of each bit of processor status register
C flag
Z flag
I flag
D flag
B flag
T flag
V flag
N flag
Set instruction
SEC
SEI
SED
SET
Clear instruction
CLC
CLI
CLD
CLT
CLV
CPU mode register
(CPUM: address 003B16, initial value: 0016)
Processor mode bits
b1b0
0 0 :
Single-chip mode
0 1 :
Not available
1 0 :
Not available
1 1 :
Not available
Stack page selection bit
0 : 0
page
1 : 1
page
Disable (returns “0” when read
)
b7
b0
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