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參數(shù)資料
| 型號： | M37542M4-XXXSP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PDIP32 |
| 封裝： | 0.400 INCH, PLASTIC, SDIP-32 |
| 文件頁數(shù)： | 44/68頁 |
| 文件大小： | 1191K |
| 代理商： | M37542M4-XXXSP |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7542 Group
MITSUBISHI MICROCOMPUTERS
49
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
[Transmit buffer register 2/receive buffer register 2 (TB2/
RB2)] 002E16
The transmit buffer register and the receive buffer register are lo-
cated at the same address. The transmit buffer is write-only and
the receive buffer is read-only. If a character bit length is 7 bits, the
MSB of data stored in the receive buffer is “0”.
[Serial I/O2 status register (SIO2STS)] 002F16
The read-only serial I/O2 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O2
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer register is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg-
ister, and the receive buffer full flag is set. A write to the serial I/O1
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O2 enable bit SIOE
(bit 7 of the serial I/O2 control register) also clears all the status
flags, including the error flags.
Bits 0 to 6 of the serial I/O2 status register are initialized to “0” at
reset, but if the transmit enable bit of the serial I/O2 control regis-
ter has been set to “1”, the transmit shift completion flag (bit 2)
and the transmit buffer empty flag (bit 0) become “1”.
[Serial I/O2 control register (SIO2CON)] 003016
The serial I/O2 control register consists of eight control bits for the
serial I/O2 function.
[UART2 control register (UART2CON)] 003116
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer and one bit (bit 4) which is al-
ways valid and sets the output structure of the P05/TxD2 pin.
[Baud rate generator 2 (BRG2)] 003216
The baud rate generator determines the baud rate for serial transfer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate generator.
s Notes on Serial I/O2
Serial I/O interrupt
When setting the transmit enable bit to “1”, the serial I/O transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronized with the transmission en-
abled, take the following sequence.
Set the serial I/O transmit interrupt enable bit to “0” (disabled).
Set the transmit enable bit to “1”.
Set the serial I/O transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
Set the serial I/O transmit interrupt enable bit to “1” (enabled).
I/O pin function when serial I/O2 is enabled.
The functions of P06 and P07 are switched with the setting values
of a serial I/O2 mode selection bit and a serial I/O2 synchronous
clock selection bit as follows.
(1) Serial I/O2 mode selection bit
→ “1” :
Clock synchronous type serial I/O is selected.
Setup of a serial I/O2 synchronous clock selection bit
“0” : P06 pin turns into an output pin of a synchronous clock.
“1” : P06 pin turns into an input pin of a synchronous clock.
Setup of a SRDY2 output enable bit (SRDY)
“0” : P07 pin can be used as a normal I/O pin.
“1” : P07 pin turns into a SRDY2 output pin.
(2) Serial I/O2 mode selection bit
→ “0” :
Clock asynchronous (UART) type serial I/O is selected.
Setup of a serial I/O2 synchronous clock selection bit
“0”: P06 pin can be used as a normal I/O pin.
“1”: P06 pin turns into an input pin of an external clock.
When clock asynchronous (UART) type serial I/O is selected, it is
P07 pin. It can be used as a normal I/O pin.
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