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| 型號： | M37542M4-XXXSP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PDIP32 |
| 封裝： | 0.400 INCH, PLASTIC, SDIP-32 |
| 文件頁數(shù)： | 25/68頁 |
| 文件大?。?/td> | 1191K |
| 代理商： | M37542M4-XXXSP |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7542 Group
MITSUBISHI MICROCOMPUTERS
31
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
Output compare
7542 group has 4-output compare channels. Each channel (0 to 3)
has the same function and can be used to output waveform by us-
ing count value of either Timer A or Timer B.
The source timer for each channel is selected by setting value of
the compare x (x = 0, 1, 2, 3) timer source bit. Timer A and Timer B
can be selected for the source timer to each channel, respectively.
To use each compare channel, set “1” to the compare x output
port bit and set the port direction register corresponding to com-
pare channel to output mode.
The compare value for each channel is set to the compare regis-
ter (low-order) and compare register (high-order).
Writing to the register for each channel is controlled by setting
value of compare register write pointer. Writing to each register is
in the following order;
1.Set the value of corresponded output compare channel to the
compare register write pointer.
2.Write a value to the compare register (low-order) and compare
register (high-order).
3.Set “1” to the compare latch y (y = 00, 01, 10, 11, 20, 21, 30, 31)
re-load bit.
When “1” is set to the compare latch y re-load bit, the value set
to the compare register is loaded to compare latch when the
next timer underflow.
When count value of timer and setting value of compare latch is
matched, compare output trigger occurs.
When “1: Enabled” is set to the compare trigger x enable bit, the
output waveform from port is inverted by compare trigger.
When “0: Disabled” is set to the compare trigger x enable bit, the out-
put waveform is not inverted, so port output can be fixed to “H” or “L”.
When “0: Positive” is set to the compare x output level latch, the
compare output waveform is turned to “H level” at compare latch
x0’s match and turned to “L level” at compare latch x1’s match.
When “1 :Negative” is set to the compare x output level latch, the
compare output waveform is turned to “L level” at compare latch
x0’s match and turned to “H level” at compare latch x1’s match.
The compare output level of each channel can be confirmed by
reading the compare x output status bit.
Compare output interrupt is available when match of each com-
pare channel and timer count value. The interrupt request from
each channel can be disabled or enabled by setting value of com-
pare latch y interrupt source bit.
Compare 0,1 (2,3) modulation mode
In compare modulation mode, modulation waveform can be gener-
ated by using compare channel 0 and 1, or compare channel 2 and 3.
To use this mode,
Set “1: Enabled” to the compare 0,1 (2, 3) modulation mode bit.
Set Timer A underflow for Timer B count source.
Set Timer A for the timer source of compare channel 0 (2).
Set Timer B for the timer source of compare channel 1 (3).
In this mode, AND waveform of compare 0 (1) and compare 2 (3)
is generated from Port P01 and P31, respectively. Accordingly, in
order to use this mode, set “1” to the compare 0 output port bit or
compare 2 output port bit.
Fig. 30 Structure of capture/compare register R/W pointer
Fig. 31 Structure of compare register re-load register
b7
b0
Compare register R/W pointer
b2 b1 b0
000 : Compare latch 00
001 : Compare latch 01
010 : Compare latch 10
011 : Compare latch 11
100 : Compare latch 20
101 : Compare latch 21
110 : Compare latch 30
111 : Compare latch 31
Not used (returns “0” when read)
Capture register 0 R/W pointer
0: Capture latch 00
1: Capture latch 01
Capture register 1 R/W pointer
0: Capture latch 10
1: Capture latch 11
Not used (returns “0” when read)
Capture/compare register R/W pointer
(CCRP : address 001216, initial value: 0016)
b7
b0
Compare latch 00, 01 re-load bit
0: Re-load disabled
1: Re-load at next underflow
Compare latch 10, 11 re-load bit
0: Re-load disabled
1: Re-load at next underflow
Compare latch 20, 21 re-load bit
0: Re-load disabled
1: Re-load at next underflow
Compare latch 30, 31 re-load bit
0: Re-load disabled
1: Re-load at next underflow
Not used (returns “0” when read)
Compare register re-load register
(CMPR : address 001416, initial value: 0016)
s Notes on Output Compare
When the selected source timer of each compare channel is
stopped, written data to compare register is loaded to the com-
pare latch simultaneously.
Do not write the same data to both of compare latch x0 and x1.
When setting value of the compare latch is larger than timer set-
ting value, compare match signal is not generated. Accordingly,
the output waveform is fixed to “L” or “H” level.
However, when setting value of another compare latch is
smaller than timer setting value, this compare match signal is
generated. Accordingly, compare match interrupt occurs.
When the compare x trigger enable bit is cleared to “0” (dis-
abled), the match trigger to the waveform output circuit is
disabled, and the output waveform can be fixed to “L” or “H”
level.
However, in this case, the compare match signal is generated.
Accordingly, compare match interrupt occurs.
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