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| 型號： | M37542M4-XXXSP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PDIP32 |
| 封裝： | 0.400 INCH, PLASTIC, SDIP-32 |
| 文件頁數(shù)： | 41/68頁 |
| 文件大?。?/td> | 1191K |
| 代理商： | M37542M4-XXXSP |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7542 Group
MITSUBISHI MICROCOMPUTERS
46
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
Bus collision detection (SIO1)
SIO1 can detect a bus collision by setting UART1 bus collision de-
tection interrupt enable bit.
When transmission is started in the clock synchronous or asyn-
chronous (UART) serial I/O mode, the transmit pin TxD1 is
compared with the receive pin RxD1 in synchronization with rising
edge of transmit shift clock. If they do not coincide with each other,
a bus collision detection interrupt request occurs.
When a transmit data collision is detected between LSB and MSB
of transmit data in the clock synchronous serial I/O mode or be-
tween the start bit and stop bit of transmit data in UART mode, a
bus collision detection can be performed by both the internal clock
and the external clock.
A block diagram is shown in Fig. 56.
A timing diagram is shown in Fig. 57.
Note: Bus collision detection can be used when SIO1 is operating
at full-duplex communication. When SIO1 is operating at
half-duplex communication, set bus collision detection inter-
rupt to be disabled.
Fig. 56 Block diagram of bus collision detection interrupt circuit
Fig. 57 Timing diagram of bus collision detection interrupt
Bus collision detection
interrupt generation
Data collision
Transmit shift clock
Transmit pin TxD1
Receive pin RxD1
D
TxD
RxD
Shift clock
UART1 bus collision detection
interrupt valid bit
(Address 000A16, bit 1)
UART1 bus collision detection
interrupt discrimination bit
(Address 000B16, bit 1)
Key-on wakeup/
UART1 bus collision detection
interrupt request bit
(Address 003C16, bit 6)
Key-on wakeup interrupt request
Q
0 : No interrupt request issued
Interrupt source set register
(INTSET: address 000A16, initial value: 0016)
Key-on wakeup interrupt valid bit
b7
b0
0: Interrupt invalid
Interrupt source discrimination register
(INTDIS: address 000B16, initial value: 0016)
Key-on wakeup interrupt discrimination bit
b7
b0
Interrupt request register 1
(IREQ1 : address 003C16, initial value : 0016)
Serial I/O1 receive interrupt request bit
b7
b0
Serial I/O1 receive interrupt enable bit
0 : Interrupts disabled
Interrupt control register 1
(ICON1 : address 003E16, initial value : 0016)
b7
b0
1 : Interrupts enabled
CNTR0 interrupt enable bit
Key-on wake up/UART1 bus collision
INT1 interrupt enable bit
INT0 interrupt enable bit
Serial I/O2 transmit interrupt enable bit
Serial I/O2 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
detection interrupt enable bit
1 : Interrupt request issued
CNTR0 interrupt request bit
detection interrupt request bit
Key-on wake up/UART1 bus collision
INT1 interrupt request bit
INT0 interrupt request bit
Serial I/O2 transmit interrupt request bit
Serial I/O2 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
1: Interrupt occurs
0: Interrupt does not occur
Not used (returns “0” when read)
Timer 1 interrupt discrimination bit
A-D conversion interrupt discrimination bit
discrimination bit
UART1 bus collision detection interrupt
1: Interrupt valid
Not used (returns “0” when read)
Timer 1 interrupt valid bit
A-D conversion interrupt valid bit
UART1 bus collision detection
interrupt valid bit
Fig. 55 Bus collision detection circuit related registers
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