參數(shù)資料
型號： M37542F8SP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDIP32
封裝： 0.400 INCH, PLASTIC, SDIP-32
文件頁數(shù)： 57/68頁
文件大?。?/td> 1191K
代理商： M37542F8SP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7542 Group
MITSUBISHI MICROCOMPUTERS
60
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
Fig. 81 State transition
Operation clock source: Ring oscillator (Note 2)
Operation clock source: f(XIN) (Note 1)
Notes on switch of clock
(1) In operation clock = f(XIN), the following can be selected for the CPU clock division ratio.
f(XIN)/2 (high-speed mode)
f(XIN)/8 (middle-speed mode)
f(XIN) (double-speed mode, only at a ceramic oscillation)
(2) In operation clock = ring oscillator, the following can be selected for the CPU clock division ratio.
ROSC/1 (ring double-speed mode)
ROSC/2 (ring high-speed mode)
ROSC/8 (ring middle-speed mode)
ROSC/128 (ring low-speed mode)
(3) Executing the state transition state 3 to 2 or state 3 to 3’ after stabilizing XIN oscillation.
(4) After system is released from reset, and state transition of state 2
→ state 3 and state transition of state 2’b → state 3’b,
ROSC/8 (ring middle-speed mode) is selected for CPU clock.
(5) “State 2’a” is prohibitive state.
Because when oscillation stop reset bit is set to “0”, internal reset does not occur.
So if clock stop is detected at “State 2’a”, MCU will be locked.
(6) STP instruction cannot be used when oscillation stop detection circuit is in active.
RESET state 2
f(XIN) oscillation: enabled
Ring oscillator: enabled
RESET state 1
f(XIN) oscillation: enabled
Ring oscillator: enabled
Oscillation stop detection circuit is in active. (Note 6)
Hardware
reset
(external
reset)
MISRG3 is cleared to “0”.
MISRG2=12
MISRG2=02
MISRG2=12
MISRG2=02
MISRG1=12
MISRG1=02
(MISRG3 is cleared to “0”.)
MISRG1=12
(Note 3)
MISRG1=02
(MISRG3 is cleared to “0”.)
State 3
State 2
f(XIN) oscillation: enabled
Ring oscillator: enabled
f(XIN) oscillation: enabled
Ring oscillator: enabled
State 3’
State 2’
f(XIN) oscillation: enabled
Ring oscillator: enabled
State 2’a (Note 5)
Oscillation stop reset disabled
When oscillation stop is detected;
MISRG3 is set to “1”.
Internal RESET does not occur.
Prohibitive state
MUC will be locked when Ceramic
or RC oscillation is stopped.
State 3’a
Oscillation stop reset disabled
When oscillation stop is detected;
MISRG3 is set to “1”.
Internal RESET does not occur.
Oscillation stop reset enabled
When oscillation stop is detected;
MISRG3 is set to “1”.
Internal RESET occurs.
Oscillation stop reset enabled
When oscillation stop is detected;
MISRG3 is set to “1”.
Internal RESET occurs.
State 3’c
Release from internal reset
MISRG3 is set to “1”.
Oscillation status can be
confirmed by reading MISRG3.
f(XIN) oscillation: enabled
Ring oscillator: enabled
State 3’b
State 2’b
CPUM76=102
(Note 4)
CPUM76=002
012
112
(Note 3)
CPUM76=102
CPUM76=002
012
112
CPUM76=102
(Note 4)
CPUM76=002
012
112
Reset
released
(Note 4)
Reset
released
(Note 4)
Oscillation stop is detected
(internal reset)
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相關代理商/技術參數(shù)
參數(shù)描述
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