參數(shù)資料
型號(hào)： M37542F8SP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDIP32
封裝： 0.400 INCH, PLASTIC, SDIP-32
文件頁(yè)數(shù)： 54/68頁(yè)
文件大?。?/td> 1191K
代理商： M37542F8SP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7542 Group
MITSUBISHI MICROCOMPUTERS
58
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
Fig. 79 State transition
STP mode
f(XIN) oscillation: stop
Ring oscillator: stop
WAIT mode 1
WAIT mode 2
WAIT mode 3
WAIT mode 3’
Operation clock source: Ring oscillator (Note 2)
Operation clock source: f(XIN) (Note 1)
Notes on switch of clock
(1) In operation clock = f(XIN), the following can be selected for the CPU clock division ratio.
f(XIN)/2 (high-speed mode)
f(XIN)/8 (middle-speed mode)
f(XIN) (double-speed mode, only at a ceramic oscillation)
(2) In operation clock = ring oscillator, the following can be selected for the CPU clock division ratio.
ROSC/1 (ring double-speed mode)
ROSC/2 (ring high-speed mode)
ROSC/8 (ring middle-speed mode)
ROSC/128 (ring low-speed mode)
(3) After system is released from reset, and state transition of state 2
→ state 3 and state transition of state 2’ → state 3’,
ROSC/8 (ring middle-speed mode) is selected for CPU clock.
(4) Executing the state transition state 3 to 2 or state 3 to 3’ after stabilizing XIN oscillation.
(5) When the state 2
→ state 3 → state 4 is performed, execute the NOP instruction as shown below
according to the division ratio of CPU clock.
1. CPUM76 = 102 (state 2
→ state 3)
2. NOP instruction
Double-speed mode: NOP 3
High-speed mode: NOP 1
Middle-speed mode: NOP 0
3. CPU4 = 12 (state 3
→ state 4)
(6) When the state 3
→ state 2 → state 1 is performed, execute the NOP instruction as shown below
according to the division ratio of CPU clock.
1. CPUM76 = 002 or 012 or 112 (state 3
→ state 2)
2. NOP instruction
TBD
3. CPU3 = 12 (state 2
→ state 1)
WAIT mode 4
State 4
RESET state
f(XIN) oscillation: enabled
Ring oscillator: enabled
State 3
State 3’
WAIT mode 2’
State 2’
State 2
State 1
Interrupt
STP
instruction
Interrupt
WIT
instruction
Interrupt
CPUM3=02
CPUM3=12
CPUM76=102
(Note 3)
CPUM76=002
012
112
(Note 4)
CPUM76=102
(Note 3)
CPUM76=002
012
112
MISRG1=12
MISRG1=02
MISRG1=12
(Note 4)
MISRG1=02
Reset
released
(Note 3)
CPUM4=02
CPUM4=12
Interrupt
WIT
instruction
WIT
instruction
Interrupt
WIT
instruction
Interrupt
WIT
instruction
Interrupt
WIT
instruction
STP
instruction
STP
instruction
STP
instruction
Interrupt
f(XIN) oscillation: enabled
Ring oscillator: stop
f(XIN) oscillation: enabled
Ring oscillator: enabled
f(XIN) oscillation: enabled
Ring oscillator: enabled
f(XIN) oscillation: enabled
Ring oscillator: enabled
f(XIN) oscillation: enabled
Ring oscillator: enabled
Oscillation stop detection circuit valid
f(XIN) oscillation: stop
Ring oscillator: enabled
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參數(shù)描述
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