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參數資料
| 型號： | M37542F8SP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDIP32 |
| 封裝： | 0.400 INCH, PLASTIC, SDIP-32 |
| 文件頁數： | 52/68頁 |
| 文件大?。?/td> | 1191K |
| 代理商： | M37542F8SP |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7542 Group
MITSUBISHI MICROCOMPUTERS
56
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
(1) Oscillation control
Stop mode
When the STP instruction is executed, the internal clock
φ stops at
an “H” level and the XIN oscillator stops. At this time, timer 1 is set
to “0116” and prescaler 1 is set to “FF16” when the oscillation sta-
bilization time set bit after release of the STP instruction is “0”. On
the other hand, timer 1 and prescaler 1 are not set when the
above bit is “1”. Accordingly, set the wait time fit for the oscillation
stabilization time of the oscillator to be used. f(XIN)/16 is forcibly
connected to the input of prescaler 1. When an external interrupt
is accepted, oscillation is restarted but the internal clock
φ remains
at “H” until timer 1 underflows. As soon as timer 1 underflows, the
internal clock
φ is supplied. This is because when a ceramic oscil-
lator is used, some time is required until a start of oscillation. In
case oscillation is restarted by reset, no wait time is generated. So
apply an “L” level to the RESET pin while oscillation becomes
stable.
Wait mode
If the WIT instruction is executed, the internal clock
φ stops at an
“H” level, but the oscillator does not stop. The internal clock re-
starts if a reset occurs or when an interrupt is received. Since the
oscillator does not stop, normal operation can be started immedi-
ately after the clock is restarted. To ensure that interrupts will be
received to release the STP or WIT state, interrupt enable bits
must be set to “1” before the STP or WIT instruction is executed.
s Notes on Clock Generating Circuit
For use with the oscillation stabilization set bit after release of the
STP instruction set to “1”, set values in timer 1 and prescaler 1 af-
ter fully appreciating the oscillation stabilization time of the
oscillator to be used.
Switch of ceramic and RC oscillations
After releasing reset the operation starts by starting a built-in ring
oscillator. Then, a ceramic oscillation or an RC oscillation is se-
lected by setting bit 5 of the CPU mode register.
Double-speed mode
When a ceramic oscillation is selected, a double-speed mode can
be used. Do not use it when an RC oscillation is selected.
CPU mode register
Bits 5, 1 and 0 of CPU mode register are used to select oscillation
mode and to control operation modes of the microcomputer. In or-
der to prevent the dead-lock by error-writing (ex. program
run-away), these bits can be rewritten only once after releasing re-
set. After rewriting it is disable to write any data to the bit. (The
emulator MCU “M37542RSS” is excluded.)
Also, when the read-modify-write instructions (SEB, CLB) are ex-
ecuted to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked.
Clock division ratio, XIN oscillation control, ring oscillator control
The state transition shown in Fig. 79 can be performed by setting
the clock division ratio selection bits (bits 7 and 6), XIN oscillation
control bit (bit 4), ring oscillator oscillation control bit (bit 3) of CPU
mode register. Be careful of notes on use in Fig. 79.
q Ring oscillation division ratio
At ring oscillator mode, division ratio of ring oscillator for CPU
clock is selected by setting value of ring oscillation division ratio
selection register. The division ratio of ring oscillation for CPU
clock is selected from among 1/1, 1/2, 1/8, 1/128. The operation
clock for the peripheral function block is not changed by setting
value of this register.
s Notes on Ring Oscillation Division Ratio
When system is released from reset, ROSC/8 (ring middle-speed
mode) is selected for CPU clock.
When state transition from the ceramic or RC oscillation to ring
oscillator, ROSC/8 (ring middle-speed mode) is selected for CPU
clock.
When the MCU operates by ring-oscillator for the main clock
without external oscillation circuit, connect XIN pin to VCC
through a resistor and leave XOUT pin open.
Set “10010x002” (x = 0 or 1) to CPUM.
Fig. 76 Structure of ring oscillation division ratio selection
register
Fig. 75 Structure of CPU mode register
Ring oscillation division ratio selection register
(RODR: address 003716, initial value: 0216)
Ring oscillator division ratio
b1 b0
00: Ring double-speed mode (ROSC/1)
01: Ring high-speed mode (ROSC/2)
10: Ring middle-speed mode (ROSC/8)
11: Ring low-speed mode (ROSC/128)
Not used (returns “0” when read)
b7
b0
Oscillation mode selection bit (Note 1)
0 : Ceramic oscillation
1 : RC oscillation
CPU mode register
(CPUM: address 003B16, initial value: 8016)
Stack page selection bit
0 : 0 page
1 : 1 page
Clock division ratio selection bits
b7 b6
0
0 : f(
φ) = f(XIN)/2 (High-speed mode)
0
1 : f(
φ) = f(XIN)/8 (Middle-speed mode)
1
0 : applied from ring oscillator
1
1 : f(
φ) = f(XIN) (Double-speed mode)(Note 2)
Ring oscillator oscillation control bit
0 : Ring oscillator oscillation enabled
1 : Ring oscillator oscillation stop
XIN oscillation control bit
0 : Ceramic or RC oscillation enabled
1 : Ceramic or RC oscillation stop
Processor mode bits (Note 1)
b1 b0
0
0 Single-chip mode
0
1
0
1
Not available
b7
b0
2: These bits are used only when a ceramic oscillation is selected.
Note 1: The bit can be rewritten only once after releasing reset. After rewriting
it is disable to write any data to the bit. However, by reset the bit is
initialized and can be rewritten, again.
(It is not disable to write any data to the bit for emulator MCU
“M37542RSS”.)
Do not use these when an RC oscillation is selected.
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