參數(shù)資料
型號(hào)： M37542F8SP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDIP32
封裝： 0.400 INCH, PLASTIC, SDIP-32
文件頁數(shù)： 47/68頁
文件大?。?/td> 1191K
代理商： M37542F8SP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7542 Group
MITSUBISHI MICROCOMPUTERS
51
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
A-D Converter
The functional blocks of the A-D converter are described below.
[A-D conversion register] AD
The A-D conversion register is a read-only register that stores the
result of A-D conversion. Do not read out this register during an A-
D conversion.
[A-D control register] ADCON
The A-D control register controls the A-D converter. Bit 2 to 0 are
analog input pin selection bits. Bit 4 is the AD conversion comple-
tion bit. The value of this bit remains at “0” during A-D conversion,
and changes to “1” at completion of A-D conversion.
A-D conversion is started by setting this bit to “0”.
[Comparison voltage generator]
The comparison voltage generator divides the voltage between
AVSS and VREF by 1024, and outputs the divided voltages.
[Channel selector]
The channel selector selects one of ports P27/AN7 to P20/AN0,
and inputs the voltage to the comparator.
[Comparator and control circuit]
The comparator and control circuit compares an analog input volt-
age with the comparison voltage and stores its result into the A-D
conversion register. When A-D conversion is completed, the con-
trol circuit sets the AD conversion completion bit and the AD
interrupt request bit to “1”. Because the comparator is constructed
linked to a capacitor, set f(XIN) to 500 kHz or more during A-D con-
version.
Fig. 63 Structure of A-D control register
Fig. 64 Structure of A-D conversion register
Fig. 65 Block diagram of A-D converter
A-D control register
(Address 0034 16)
Channel
selector
A-D control circuit
Resistor ladder
VREF
Comparator
A-D interrupt request
b7
b0
Data bus
3
10
P20/AN0
P21/AN1
P22/AN2
P23/AN3
P24/AN4
P25/AN5
P26/AN6
P27/AN7
A-D conversion register (low-order)
(Address 0036 16)
(Address 0035 16)
A-D conversion register (high-order)
VSS
Read 8-bit (Read only address 003516)
b7
b0
b9
b8
b7
b6
b5
b4
b3
b2
(Address 003516)
Read 10-bit (read in order address 003616, 003516)
b7
b0
b9
b8
(Address 003616)
b7
b0
b7
b6
b5
b4
b3
b2
b1
b0
(Address 003516)
Note: High-order 6-bit of address 003616 returns “0” when read.
Not used (returns “0” when read)
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
b7
b0
Analog input pin selection bits
000 : P20/AN0
001 : P21/AN1
010 : P22/AN2
011 : P23/AN3
100 : P24/AN4
101 : P25/AN5
110 : P26/AN6 (Note)
111 : P27/AN7 (Note)
Note: These can be used only for 36 pin version.
A-D control register
(ADCON : address 003416, initial value: 1016)
Not used (Do not write “1” to this bit.)
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