Feb 18, 2005
page 62 of 85
REJ03B0122-0101
7512 Group
Outline Performance (CPU Rewrite Mode)
CPU rewrite mode is usable in the single-chip or Boot mode. The
only User ROM area can be rewritten in CPU rewrite mode.
In CPU rewrite mode, the CPU erases, programs and reads the in-
ternal flash memory by executing software commands. This
rewrite control program must be transferred to the RAM before it
can be executed.
The MCU enters CPU rewrite mode by setting “1” to the CPU Rewrite
Mode Select Bit (bit 1 of address 0FE016). Software commands are
accepted once the mode is entered.
Use software commands to control program and erase operations.
Whether a program or erase operation has terminated normally or
in error can be verified by reading the status register.
Figure 69 shows the flash memory control register 0.
Bit 0 is the RY/BY status flag used exclusively to read the operat-
ing status of the flash memory. During programming and erase
operations, it is “0” (busy). Otherwise, it is “1” (ready).
Bit 1 is the CPU Rewrite Mode Select Bit. When this bit is set to
“1”, the MCU enters CPU rewrite mode. Software commands are
accepted once the mode is entered. In CPU rewrite mode, the
CPU becomes unable to access the internal flash memory directly.
Fig. 69 Structure of flash memory control register
Flash memory control register 0 (address 0FE016)
FMCR0
RY/BY status flag
0: Busy (being programmed or erased)
1: Ready
CPU rewrite mode select bit (Note 1)
0: Normal mode
1: CPU rewrite mode
8 KB user block E/W enable bit (UBEWEN) (Note 1, 2)
0: E/W disable
1: E/W enable
Flash memory reset bit (Note 3,4)
0: Normal operation
1: Reset
Not used (“0” at write)
User ROM area selection bit (Note 5)
0: Boot ROM area accessed
1: User ROM area accessed
Program status flag
0: Passed
1: Error
Erase status flag
0: Passed
1: Error
b0
b7
Notes
1: For this bit to be set to “1”, the user needs to write “0” and then “1” to it in succession.
To reset this bit “0”, only write “0”.
2: This bit is valid when the CPU rewrite mode select bit is “1”.
3: This bit is valid when the CPU rewrite mode select bit is “1”. Fix this bit “0” when the CPU
rewrite mode select bit is “0”.
4: Setting this bit “1” (Resetting the flash memory control circuit), access to the flash memory
is disabled for 10
sec.
5: Writing this bit must be executed in the RAM.
Therefore, use the control program in the RAM for write to bit 1. To
set this bit to “1”, it is necessary to write “0” and then write “1” in
succession. The bit can be set to “0” by only writing “0”.
Bit 2 is 8KB user block E/W enable bit. Setting this bit and bit 4 (All
user block E/W enable bit) of the flash memory control register 2
(0FE216) according to the table T-3, E/W protect is done at CPU
Rewrite mode for User block
Bit 3 is the flash memory reset bit used to reset the control circuit of
internal flash memory. This bit is used when exiting CPU rewrite
mode and when flash memory access has failed. When the CPU
Rewrite Mode Select Bit is “1”, setting “1” for this bit resets the con-
trol circuit. To release the reset, it is necessary to set this bit to “0”.
Bit 5 is User ROM area selection bit, and this bit is only available
in Boot mode. Setting this bit “1”, User ROM area can be ac-
cessed, and CPU rewrite is available.
Bit 6 is the program status flag, and this flag changes “1” when
flash memory write operation ends at abnormal state. If program
error occurs, corresponding block is not available.
Bit 7 is the erase status flag, and this flag changes “1” when flash
memory erase operation ends at abnormal state. If erase error oc-
curs, corresponding block is not available.