參數(shù)資料
型號(hào)： M37512F8H-XXXHP
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PQFP48
封裝： 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件頁(yè)數(shù)： 53/87頁(yè)
文件大?。?/td> 879K
代理商： M37512F8H-XXXHP
Feb 18, 2005
page 57 of 85
REJ03B0122-0101
7512 Group
Fig. 66 Structure of MISRG1, MISRG2
MISRG2(003716)
Analog in additional bit
bit0 ADCON
(003416)
bit2 bit1 bit0
0
XXX
P35/AN5 - P30/AN0
1
000
P04/AN8
1
001
P05/AN9
1
010
P06/AN10
1
011
P07/AN11
1
X
Inhibit
b7
b0
32kHz RC oscillation calibration enable bit (Note 4)
0: Oscillating
1: Enable
High-speed RC oscillation stop bit (Note4)
0: Oscillating
1: Stopping
XIN switching inhibit bit (Note3, 4)
0: Enable switch to XIN
1: Disable switch to XIN
32kHz RC oscillation enable bit (Note4)
0: XCIN-XCOUT oscillation
1: 32kHz RC oscillation
Serial I/O2 clock source selection bit (When low-speed mode)
0: XCIN
1: Built-in oscillator for SI/O2
Integrate coefficient selection bit of current integrate control
register (000E16) protect bit
0: Write disable
1: Write enable
Reserved (do not write "1")
Note 3: When this bit is set to "1", it cannot be rewritten to "0" by program.
Note 4: This bit is protected.
MISRG(003816)
Oscillation stabilizing time set after STP instruction
released bit
0: Automatically set “0116” to Timer 1,
FF16” to Prescaler 12
1: Automatically set nothing
Middle-speed mode automatic switch set bit
0: Not set automatically
1: Automatic switching enable (Note1, 2)
Middle-speed mode automatic switch wait time set bit
0: 4.5 to 5.5 machine cycles
1: 6.5 to 7.5 machine cycles
Middle-speed mode automatic switch start bit
(Depending on program)
0: Invalid
1: Automatic switch start (Note2)
Charge over current detect control register (0FF016) protect.bit
0:Write disable
1:Write enable
Over current detect time set up register 2 (001416) protect bit
0:Write disable
1:Write enable
Not used (returns “0” when read)
b7
b0
Note 1: The microcomputer can be switched to the middle-speed mode automatically by the
SCL/SDA interrupt during operation in the low-speed mode.
Note 2: When switching from the low-speed mode to the middle-speed mode, the value of the
CPU mode register also changes.
sNotes on middle-speed mode switch set bit
When the middle-speed mode automatic switch set bit is set to “1”
during operation in the low-speed mode, XIN oscillation starts au-
tomatically by detecting the rising edge or the falling edge of the
SCL pin or the SDA pin and the microcomputer switch to the
middle-speed mode. Select the timing which switches from the
low-speed mode to the middle-speed mode by the middle-speed
mode automatic switch wait time set bit. The timing is selectable
from 4.5 to 5.5 cycles or 6.5 to 7.5 cycles in the low-speed mode.
Select according to the oscillation start characteristic of the oscil-
lator of XIN to be used. By writing “1” in the middle-speed mode
automatic switch start bit during operation in the low-speed mode,
XIN oscillation starts automatically and the microcomputer
changes to the middle-speed mode.
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