參數(shù)資料
型號(hào): M37281EKSP
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述: 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器
文件頁(yè)數(shù): 78/172頁(yè)
文件大?。?/td> 1319K
代理商: M37281EKSP
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M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP
Rev.1.01 2003.07.16 page 78 of 170
8.11.3 Dot Size
The dot size can be selected by a block unit. The dot size in vertical
direction is determined by dividing H
SYNC
in the vertical dot size con-
trol circuit. The dot size in horizontal is determined by dividing the
following clock in the horizontal dot size control circuit : the clock
gained by dividing the OSD clock source (data slicer clock, OSC1,
main clock) in the pre-divide circuit. The clock cycle divided in the
pre-divide circuit is defined as 1T
C
.
The dot size is specified by bits 6 to 3 of the block control register.
Fig. 8.11.14 Block Diagram of Dot Size Control Circuit
Fig. 8.11.15 Definition of Dot Sizes
H
SYNC
Synchronous
circuit
Cycle
2
Cycle
3
Pre-divide circuit
Clock cycle
= 1T
C
Horizontal dot size
control circuit
Vertical dot size
control circuit
OSD control circuit
OSC1
Note:
To use data slicer clock, set bit 0 of data slicer control register 1 to
1.
Data slicer clock
(See note)
1 dot
Scanning line of F1 (F2)
Scanning line of F2 (F1)
1/2H
1H
2H
3H
3T
C
2T
C
1T
C
1T
C
In normal scan mode
Refer to Figure 8.11.4 (the block control register i), refer to Figure
8.11.6 (the clock control register).
The block diagram of dot size control circuit is shown in Figure 8.11.14.
Notes 1:
The pre-divide ratio = 3 cannot be used in the CC mode.
2:
The pre-divide ratio of the layer 2 must be same as that of the layer 1
by the block control register i.
3:
In the bi-scan mode, the dot size in the vertical direction is 2 times as
ompared with the normal mode. Refer to
8.11.13 Scan Mode
about
the scan mode.
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