參數(shù)資料
型號： M37281EKSP
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述： 單芯片8位CMOS微機隱蔽字幕解碼器和屏幕顯示控制器
文件頁數(shù)： 18/172頁
文件大?。?/td> 1319K
代理商： M37281EKSP
M37281MAH
–
XXXSP,M37281MFH
–
XXXSP,M37281MKH
–
XXXSP, M37281EKSP
Rev.1.01 2003.07.16 page 18 of 170
Fig. 8.2.7 Memory Map of Special Function Register 2 (SFR2) (2)
2
2
232
16
2
3
1
2
4
1
235
16
2
6
1
2
7
1
238
16
2
9
1
2
A
1
2
B
1
23C
16
23D
16
2
E
1
2
F
1
3
3
0
1
1
1
6
6
3
3
6
6
3
3
6
6
3
3
3
6
6
6
3
3
6
6
221
16
2
1
3
1
4
1
225
16
226
16
7
1
8
1
229
16
22A
16
V
2
0
1
6
2
2
2
6
6
6
2
2
6
6
22C
16
D
1
E
1
22F
16
2
B
1
6
2
2
6
6
e
V
e
r
r
t
t
i
i
c
c
a
a
l
l
p
p
o
o
s
s
i
i
t
t
i
i
o
o
n
n
r
r
e
e
g
g
i
i
s
s
t
t
e
e
r
r
1
1
1
1
1
(
(
V
V
P
P
1
1
1
1
1
)
2
)
Vertical position register 1
3
(VP1
3
)
V
r
t
i
c
a
l
p
o
s
i
t
i
o
n
r
Vertical position register 1
7
(VP1
7
)
V
r
t
i
c
a
l
p
o
s
i
t
i
o
n
r
V
Vertical position register 1
6
(VP1
6
)
e
r
t
i
c
a
l
p
o
s
i
t
i
o
n
r
e
g
i
s
t
e
r
1
5
(
V
P
1
5
)
V
Vertical position register 1
2
(VP1
2
)
e
r
t
i
c
a
l
p
o
s
i
t
i
o
n
r
e
g
i
s
t
e
r
1
1
(
V
P
1
1
)
V
Vertical position register 1
10
(VP1
10
)
e
r
t
i
c
a
l
p
o
s
i
t
i
o
n
r
e
g
i
s
t
e
r
1
9
(
V
P
1
9
)
e
e
g
i
s
t
e
r
1
4
(
V
P
1
4
)
2
e
e
g
i
s
t
e
r
1
8
(
V
P
1
8
)
V
V
e
e
r
r
t
t
i
i
c
c
a
a
l
l
p
p
o
o
s
s
i
i
t
t
i
i
o
o
n
n
r
r
e
e
g
g
i
i
s
s
t
t
e
e
r
r
2
3
2
4
(
(
V
V
P
P
2
3
)
2
4
)
V
e
e
r
t
i
c
a
l
p
o
s
i
t
i
o
n
r
e
g
i
s
t
e
r
2
7
2
8
(
(
V
P
2
7
)
P
2
8
)
Vertical position register 2
5
(VP2
5
)
V
r
t
i
c
a
l
p
o
s
i
t
i
o
n
r
e
e
g
i
s
t
e
r
2
6
(
V
P
2
6
)
V
Vertical position register 2
2
(VP2
2
)
e
r
t
i
c
a
l
p
o
s
i
t
i
o
n
r
e
g
i
s
t
e
r
2
1
(
V
P
2
1
)
V
V
Vertical position register 2
11
(VP2
11
)
e
e
r
r
t
t
i
i
c
c
a
a
l
l
p
p
o
o
s
s
i
i
t
t
i
i
o
o
n
n
r
r
e
e
g
g
i
i
s
s
t
t
e
e
r
r
2
9
2
1
(
V
(
P
V
2
9
)
P
2
1
0
0
)
V
V
e
e
r
r
t
t
i
i
c
c
a
a
l
l
p
p
o
o
s
s
i
i
t
t
i
i
o
o
n
n
r
r
e
e
g
g
i
i
s
s
t
t
e
e
r
r
2
1
2
1
2
(
(
V
V
P
P
2
1
2
1
2
)
3
)
V
r
t
i
c
a
l
p
o
s
i
t
i
o
n
r
e
g
i
s
t
e
r
V
I
S
F
R
2
a
r
e
a
(
a
d
d
r
e
s
s
e
s
2
2
0
1
6
t
<
B
o
i
2
t
3
a
F
1
l
o
6
)
a
A
d
d
r
e
s
s
R
e
g
i
s
t
e
r
Bit allocation
State immediately after reset
b0 b
:
:
F
(
F
(
i
x
o
t
n
o
t
t
h
i
s
b
i
t
i
t
t
t
o
o
“
“
0
1
”
”
)
d
o
w
r
e
:
l
c
t
i
o
n
>
<
State immediately after reset
>
0
1
1
”
i
m
m
e
d
F
u
n
c
t
i
o
n
b
i
t
:
No function bit
i
x
o
t
n
o
t
t
h
i
s
b
i
t
i
t
t
t
o
o
“
“
1
0
”
”
)
d
o
w
r
e
Name
:
:
“
0
”
immediately after reset
:
i
a
t
:
I
n
f
d
t
e
e
t
e
r
r
m
s
i
n
t
a
t
e
i
m
m
e
d
i
a
t
e
l
y
a
r
e
e
“
e
l
y
a
f
t
e
r
r
e
s
e
t
1
0
V
V
e
e
r
r
t
t
i
i
c
c
a
a
l
l
p
p
o
o
s
s
i
i
t
t
i
i
o
o
n
n
r
r
e
e
g
g
i
i
s
s
t
t
e
e
r
r
2
1
2
1
4
(
(
V
V
P
P
2
1
2
1
4
)
5
)
3
V
e
r
t
i
c
a
l
p
o
s
i
t
i
o
n
r
e
g
i
s
t
e
r
2
1
6
(
V
P
2
1
6
)
5
Vertical position register 1
13
(VP1
13
)
V
r
t
i
c
a
l
p
o
s
i
t
i
o
n
r
e
e
g
i
s
t
e
r
1
1
4
(
V
P
1
1
4
)
Vertical position register 1
15
(VP1
15
)
Vertical position register 1
16
(VP1
16
)
b7
7
b
0
VP1
1
2
VP1
1
3
P
1
2
3
V
P
1
3
3
VP1
1
4
VP1
1
5
VP1
2
5
VP1
3
5
VP1
4
5
VP1
5
5
VP1
6
5
VP1
7
5
VP1
8
5
VP1
9
5
VP1
10
5
P
1
1
P
1
1
VP1
1
6
VP1
1
7
VP1
2
2
VP1
3
2
V
VP1
2
4
VP1
3
4
VP1
2
6
VP1
3
6
VP1
2
7
VP1
3
7
VP1
4
2
VP1
5
2
VP1
4
3
V
P
1
5
3
P
1
6
3
VP1
7
3
P
1
8
3
V
P
1
9
3
VP1
4
4
VP1
5
4
VP1
4
6
VP1
5
6
VP1
4
7
VP1
5
7
VP1
6
2
VP1
7
2
V
VP1
6
4
VP1
7
4
VP1
6
6
VP1
7
6
VP1
6
7
VP1
7
7
VP1
8
2
VP1
9
2
V
VP1
8
4
VP1
9
4
VP1
8
6
VP1
9
6
VP1
8
7
VP1
9
7
VP1
10
2
P
1
1
P
1
1
VP1
10
3
VP1
10
4
P
1
1
P
1
1
VP1
10
6
P
1
1
P
1
1
VP1
10
7
P
1
1
P
1
1
V
1
2
VP1
11
3
V
1
4
V
1
5
V
1
6
V
1
7
VP1
1
1
VP1
2
1
VP1
3
1
VP1
4
1
VP1
5
1
VP1
6
1
VP1
7
1
VP1
8
1
VP1
9
1
VP1
10
1
P
1
1
P
1
1
V
1
1
V
2
1
V
2
2
VP1
12
3
V
2
4
V
2
5
V
2
6
V
2
7
V
P
2
1
0
V
P
2
1
1
VP2
2
0
V
P
2
2
1
VP2
3
0
P
2
4
0
P
2
5
0
P
2
6
0
P
2
7
0
P
2
8
0
P
2
9
0
VP2
3
1
P
2
4
1
P
2
5
1
P
2
6
1
V
V
V
V
V
V
V
V
P
2
7
1
V
V
P
2
8
1
V
V
P
2
9
1
VP2
10
0
P
2
1
P
2
1
P
2
1
P
2
1
P
2
1
P
2
1
VP2
10
1
P
2
1
P
2
1
P
2
1
P
2
1
P
2
1
P
2
1
V
1
0
V
1
1
V
2
0
V
2
1
VP1
1
0
P
1
2
0
V
P
1
3
0
V
VP1
4
0
V
P
1
5
0
P
1
6
0
VP1
7
0
P
1
8
0
V
P
1
9
0
V
V
VP1
10
0
VP1
11
0
VP1
12
0
V
3
0
V
3
1
V
4
0
V
4
1
V
5
0
V
5
1
V
6
0
V
6
1
V
P
1
1
4
2
VP1
14
3
V
P
1
1
4
4
V
P
1
1
4
5
V
P
1
1
4
6
V
P
1
1
4
7
V
P
1
1
5
2
VP1
15
3
V
P
1
1
5
4
V
P
1
1
5
5
V
P
1
1
5
6
V
P
1
1
5
7
VP1
16
2
VP1
16
3
VP1
16
4
VP1
16
5
VP1
16
6
VP1
16
7
VP1
14
0
VP1
15
0
VP1
16
0
V
P
1
1
4
1
V
P
1
1
5
1
VP1
16
1
VP1
13
1
VP1
13
2
VP1
13
3
VP1
13
4
VP1
13
5
VP1
13
6
VP1
13
7
VP1
13
0
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