參數(shù)資料
型號： M37281EKSP
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述： 單芯片8位CMOS微機隱蔽字幕解碼器和屏幕顯示控制器
文件頁數(shù)： 21/172頁
文件大小： 1319K
代理商： M37281EKSP
Rev.1.01 2003.07.16 page 21 of 170
M37281MAH
–
XXXSP,M37281MFH
–
XXXSP,M37281MKH
–
XXXSP, M37281EKSP
8.3 INTERRUPTS
Interrupts can be caused by 19 different sources consisting of 3 ex-
ternal, 14 internal, 1 software, and reset. Interrupts are vectored in-
terrupts with priorities as shown in Table 8.3.1. Reset is also included
in the table because its operation is similar to an interrupt.
When an interrupt is accepted,
x
The contents of the program counter and processor status register
are automatically stored into the stack.
The interrupt disable flag I is set to
“
1
”
and the corresponding
interrupt request bit is set to
“
0.
”
The jump destination address stored in the vector address enters
the program counter.
Nothing to stop reset.
Other interrupts are disabled when the interrupt disable flag is set to
“
1.
”
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit. The interrupt request bits are
in interrupt request registers 1 and 2 and the interrupt enable bits are
in interrupt control registers 1 and 2. Figures 8.3.2 to 8.3.6 show the
interrupt-related registers.
Interrupts other than the BRK instruction interrupt and reset are ac-
cepted when the interrupt enable bit is
“
1,
”
interrupt request bit is
“
1,
”
and the interrupt disable flag is
“
0.
”
The interrupt request bit can be
set to
“
0
”
by a program, but not set to
“
1.
”
The interrupt enable bit can
be set to
“
0
”
and
“
1
”
by a program.
Reset is treated as a non-maskable interrupt with the highest priority.
Figure 8.3.1 shows interrupt control.
8.3.1 Interrupt Causes
(1) V
SYNC
and OSD Interrupts
The V
SYNC
interrupt is an interrupt request synchronized with
the vertical sync signal.
The OSD interrupt occurs after character block display to the
CRT is completed.
(2) INT1, INT2 External Interrupts
The INT1 and INT2 interrupts are external interrupt inputs, the
system detects that the level of a pin changes from LOW to HIGH
or from HIGH to LOW, and generates an interrupt request. The
input active edge can be selected by bits 3 and 4 of the interrupt
input polarity register (address 0212
16
) : when this bit is
“
0,
”
a
change from LOW to HIGH is detected; when it is
“
1,
”
a change
from HIGH to LOW is detected. Note that both bits are cleared to
“
0
”
at reset.
(3) Timer 1 to 4 Interrupts
An interrupt is generated by an overflow of timer 1, 2, 3 or 4.
Vector Addresses
FFFF
16
, FFFE
16
FFFD
16
, FFFC
16
FFFB
16
, FFFA
16
FFF9
16
, FFF8
16
FFF7
16
, FFF6
16
FFF5
16
, FFF4
16
FFF3
16
, FFF2
16
FFF1
16
, FFF0
16
FFEF
16
, FFEE
16
FFED
16
, FFEC
16
FFEB
16
, FFEA
16
FFE9
16
, FFE8
16
FFE7
16
, FFE6
16
FFE5
16
, FFE4
16
FFE3
16
, FFE2
16
FFDF
16
, FFDE
16
Interrupt Source
Reset
OSD interrupt
INT1 external interrupt
Data slicer interrupt
Serial I/O interrupt
Timer 4 interrupt
f(X
IN
)/4096
SPRITE OSD interrupt
V
SYNC
interrupt
Timer 3 interrupt
Timer 2 interrupt
Timer 1 interrupt
A-D convertion
INT3 external interrupt
INT2 external interrupt
Multi-master I
2
C-BUS interface interrupt
Timer 5
6 interrupt
BRK instruction interrupt
Remarks
Non-maskable
Active edge selectable
Software switch by software (See note)
Software switch by software (See note)/
When selecting INT3 interrupt, active edge selectable.
Active edge selectable
Software switch by software (See note)
Non-maskable (software interrupt)
Table 8.3.1 Interrupt Vector Addresses and Priority
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Note :
Switching a source during a program causes an unnecessary interrupt occurs. Accordingly, set a source at initializing of program.
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