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參數(shù)資料
| 型號(hào)： | M37274MA-XXXSP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, MICROCONTROLLER, PDIP52 |
| 封裝： | 0.600 INCH, 1.778 MM PITCH, SHRINK, PLASTIC, DIP-52 |
| 文件頁數(shù)： | 65/131頁 |
| 文件大?。?/td> | 2049K |
| 代理商： | M37274MA-XXXSP |
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39
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37274MA-XXXSP
PRELIMINARY
Notice:
This
is not
a final
specification.
Some
paramentic
limits
are
subject
to change.
MITSUBISHI MICROCOMPUTERS
After a falling of the clock run-in pulse set in bits 2 to 0 of clock run-
in detect register 2 (address 00E916) is detected, a start bit is
detected by sampling a comparator output. A sampling clock for
sampling is obtained by dividing the reference clock generated in
the timing signal generating circuit by 13.
Figure 34 shows the structure of clock run-in detect register 2.
The contents of bits 2 to 0 of clock run-in detect register 2 and bit
1 of clock run-in register 2 are written at a falling of the horizontal
synchronous signal. For this reason, even if an instruction for setting
is executed, the contents of the register cannot be rewritten until a
falling of the horizontal synchronous signal.
Fig. 33. Clock Run-in Register 2
(8) Clock run-in determination circuit
This circuit sets a window in the clock run-in portion in the composite
video signal, and then determinates clock run-in by counting the
number of pulses in this window. Set the time from a falling of the
horizontal synchronizing signal to a start of the window by bits 0 to 5
of the window register (address 00E216; refer to Figure 35). The
window ends according to the contents of the setting of the start bit
position register (refer to Figure 32).
Fig. 35. Window Register
Fig. 34. Clock Run-in Detect Register 2
70
1
Start bit detecting method
selection bit
0 : Method 1
1 : Method 2
Clock run-in register 2
(CR2 : address 00E7 16)
Fix this bit to “1”
Fix these bits to “100111 2”
0 0111
1
70
Clock run-in pulses for sampling
b2 b1 b0
0
0 : Not available
0
1 : 1st pulse
0
1
0 : 2nd pulse
0
1
1 : 3rd pulse
1
0
0 : 4th pulse
1
0
1 : 5th pulse
1
0 : 6th pulse
1
1 : 7th pulse
Clock run-in detect register 2
(CRD2 : address 00E916)
Data clock generating time
Time from detection of a start bit
to occurrence of a data clock
= (13 + set value) ! reference
clock period
70
Window start time
Time from a falling of the
horizontal synchronizing signal
to a start of the window = 4 ! set
value (“0016” to “3F16”) ! reference
clock period
Window register
(WN : address 00E216)
Fix these bits to “0”
00
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