參數(shù)資料
型號(hào): M37273MFH-XXXSP
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述: 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器
文件頁數(shù): 93/130頁
文件大小: 1663K
代理商: M37273MFH-XXXSP
92
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37273MFH–XXXSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.0
8.13. RESET CIRCUIT
When the oscillation of a quartz-crystal oscillator or a ceramic reso-
nator is stable and the power source voltage is 5 V ± 10 %, hold the
RESET pin at LOW for 2
μ
s or more, then return is to HIGH. Then, as
shown in Figure 8.13.2, reset is released and the program starts form
the address formed by using the content of address FFFF
16
as the
high-order address and the content of the address FFFE
16
as the
low-order address. The internal state of microcomputer at reset are
shown in Figures 8.2.3 to 8.2.6.
An example of the reset circuit is shown in Figure 8.13.1.
The reset input voltage must be kept 0.9 V or less until the power
source voltage surpasses 4.5 V.
Fig.8.13.2 Reset Sequence
Fig.8.13.1 Example of Reset Circuit
P
o
w
e
r
s
o
u
r
c
e
v
o
l
t
a
g
e
0
V
R
e
s
e
t
i
n
p
u
t
v
o
l
t
a
g
e
0
V
4
.
5
V
0
.
9
V
P
o
w
e
r
o
n
V
c
c
RESET
V
s
s
M
i
c
r
o
c
o
m
p
u
t
e
r
1
5
4
3
0.1
μ
F
M
5
1
9
5
3
A
L
X
IN
φ
RESET
In
t
e
r
n
a
l
R
E
S
E
T
S
Y
N
C
Address
D
a
t
a
32768 count of X
IN
clock cycle (See note 3)
Reset address from the vector table
01, S
01, S-1 01, S-2
FFFE
F
F
F
A
A
D
H
,
D
L
A
D
L
A
D
H
Notes 1
:
f(X
IN
) and f(
φ
) are in the relation : f(X
IN
) = 2·f (
φ
).
2 :
A question mark () indicates an undefined state that
depends on the previous state.
3 :
Immediately after a reset, timer 3 and timer 4 are
connected by hardware. At this time, “FF
16
” is set
in timer 3 and “07
16
” is set to timer 4. Timer 3 counts down
with f(X
IN
)/16, and reset state is released by the timer 4
overflow signal.
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