參數(shù)資料
型號: M37151M6-XXXFP
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述: 單芯片8位CMOS微機隱蔽字幕解碼器和屏幕顯示控制器
文件頁數(shù): 54/139頁
文件大?。?/td> 1491K
代理商: M37151M6-XXXFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
MITSUBISHI MICROCOMPUTERS
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
53
Rev 1.0
8.10.5 Timing Signal Generating Circuit
This circuit generates a reference clock which is 832 times as large
as the horizontal synchronous signal frequency. It also generates
various timing signals on the basis of the reference clock, horizontal
synchronous signal and vertical synchronizing signal. The circuit
operates by setting bit 0 of data slicer control register 1 (address
00E0
16
) to “1.”
The reference clock can be used as a display clock for the OSD
function in addition to the data slicer. The H
SYNC
signal can be used
as a count source instead of the composite sync signal. However,
when the H
SYNC
signal is selected, the data slicer cannot be used. A
count source of the reference clock can be selected by bit 2 of data
slicer control register 1 (address 00E0
16
).
For pins HLF, connect a resistor and a capacitor as shown in Figure
8.10.1. Make the length of wiring which is connected to these pins as
short as possible to prevent a leakage current from being generated.
Note:
It takes a few tens of milliseconds until the reference clock becomes
stable after the data slicer and the timing signal generating circuit are
started. In this period, various timing signals, H
sep
signals and V
sep
sig-
nals become unstable. For this reason, take stabilization time into con-
sideration when programming.
Fig. 8.10.7 Determination of V-pulse Waveform
Composite
sync signal
A
B
0
1
1
Bit 5 of
DSC2
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