參數(shù)資料
型號: M37151M6-XXXFP
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述: 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器
文件頁數(shù): 38/139頁
文件大小: 1491K
代理商: M37151M6-XXXFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
MITSUBISHI MICROCOMPUTERS
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
37
Rev 1.0
8.6.6 START Condition Generation Method
When the ESO bit of the I
2
C control register (address 00F9
16
) is “1,”
execute a write instruction to the I
2
C status register (address 00F8
16
)
to set the MST, TRX and BB bits to “1.” A START condition will then
be generated. After that, the bit counter becomes “000
2
” and an SCL
is output for 1 byte. The START condition generation timing and BB
bit set timing are different in the standard clock mode and the high-
speed clock mode. Refer to Figure 8.6.10 for the START condition
generation timing diagram, and Table 8.6.2 for the START condition/
STOP condition generation timing table.
Fig. 8.6.10 START Condition Generation Timing Diagram
I
2
C
w
C
D
t
s
e
t
a
s
t
g
u
s
n
r
l
e
g
i
s
t
e
r
r
i
i
a
H
o
l
d
t
i
m
e
Setup
time
S
L
S
A
BB flag
S
o
e
r
t
B
t
B
i
m
f
e
l
a
g
f
8.6.7 STOP Condition Generation Method
When the ESO bit of the I
2
C control register (address 00F9
16
) is “1,”
execute a write instruction to the I
2
C status register (address 00F8
16
)
to set the MST bit and the TRX bit to “1” and the BB bit to “0”. A STOP
condition will then be generated. The STOP condition generation tim-
ing and the BB flag reset timing are different in the standard clock
mode and the high-speed clock mode. Refer to Figure 8.6.11 for the
STOP condition generation timing diagram, and Table 8.6.2 for the
START condition/STOP condition generation timing table.
Fig. 8.6.11 STOP Condition Generation Timing Diagram
Table 8.6.2 START Condition/STOP Condition Generation Tim-
ing Table
Item
Setup time
(START condition)
Setup time
(STOP condition)
Hold time
Set/reset time
for BB flag
Standard Clock Mode
5.0
μ
s (20 cycles)
4.25
μ
s (17 cycles)
5.0
μ
s (20 cycles)
3.0
μ
s (12 cycles)
High-speed Clock Mode
2.5
μ
s (10 cycles)
1.75
μ
s (7 cycles)
2.5
μ
s (10 cycles)
1.5
μ
s (6 cycles)
Note:
Absolute time at
φ
= 4 MHz. The value in parentheses denotes the
number of
φ
cycles.
I
2
C
w
t
s
e
t
a
s
t
g
u
s
n
r
l
e
g
i
s
t
e
r
r
i
i
a
H
o
l
d
t
i
m
e
S
e
t
t
u
e
p
i
m
SCL
D
B
S
A
f
l
a
g
Reset time
for BB flag
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