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參數(shù)資料
| 型號(hào)： | M36WT864T85ZA6T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product |
| 中文描述： | 64兆位4Mb的x16插槽，多銀行，突發(fā)閃存和8兆位的SRAM為512k x16，內(nèi)存產(chǎn)品多 |
| 文件頁數(shù)： | 9/92頁 |
| 文件大?。?/td> | 624K |
| 代理商： | M36WT864T85ZA6T |
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M36WT864TF, M36WT864BF
SIGNAL DESCRIPTIONS
See Figure 2 Logic Diagram and Table 1,Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A18).
Addresses
are common inputs for the Flash and the SRAM
components. The Address Inputs select the cells
in the memory array to access during Bus Read
operations. During Bus Write operations they con-
trol the commands sent to the Command Interface
of the internal state machine. The Flash memory is
accessed through the Chip Enable (
EF
) and Write
Enable (WF) signals, while the SRAM is accessed
through two Chip Enable signals (E1S and E2S)
and the Write Enable signal (WS).
Address Inputs (A19-A21).
Addresses A19-A21
are inputs for the Flash component only. The
Flash memory is accessed through the Chip En-
able (EF) and Write Enable (WF) signals.
Data Input/Output (DQ0-DQ15).
The Data I/O
outputs the data stored at the selected address
during a Bus Read operation or inputs a command
or the data to be programmed during a Write Bus
operation.
Flash Chip Enable (EF).
The Chip Enable input
activates the memory control logic, input buffers,
decoders and sense amplifiers. When Chip En-
able is at V
IL
and Reset is at V
IH
the device is in ac-
tive mode. When Chip Enable is at V
IH
the
memory is deselected, the outputs are high imped-
ance and the power consumption is reduced to the
stand-by level.
Flash Output Enable (GF).
The Output Enable
controls data outputs during the Bus Read opera-
tion of the memory.
Flash Write Enable (
WF
).
The
controls the Bus Write operation of the memory’s
Command Interface. The data and address inputs
are latched on the rising edge of Chip Enable or
Write Enable whichever occurs first.
Flash Write Protect (WPF).
Write Protect is an
input that gives an additional hardware protection
for each block. When Write Protect is at V
IL
, the
Lock-Down is enabled and the protection status of
the Locked-Down blocks cannot be changed.
When Write Protect is at V
IH
, the Lock-Down is
disabled and the Locked-Down blocks can be
locked or unlocked. (refer to Table 13, Lock Sta-
tus).
Flash Reset (RPF).
The Reset input provides a
hardware reset of the memory. When Reset is at
V
IL
, the memory is in reset mode: the outputs are
high impedance and the current consumption is
reduced to the Reset Supply Current I
DD2
. Refer to
Table 2, DC Characteristics - Currents for the val-
ue of I
DD2.
After Reset all blocks are in the Locked
state and the Configuration Register is reset.
A0-A18
Write
Enable
When Reset is at V
IH
, the device is in normal op-
eration. Exiting reset mode the device enters
asynchronous read mode, but a negative transi-
tion of Chip Enable or Latch Enable is required to
ensure valid data outputs.
The Reset pin can be interfaced with 3V logic with-
out any additional circuitry. It can be tied to V
RPH
(refer to Table 19, DC Characteristics).
Flash Latch Enable (LF).
Latch Enable latches
the address bits on its rising edge. The address
latch is transparent when Latch Enable is at V
IL
and it is inhibited when Latch Enable is at V
IH
.
Latch Enable can be kept Low (also at board level)
when the Latch Enable function is not required or
supported.
Flash Clock (KF).
The clock input synchronizes
the Flash memory to the microcontroller during
synchronous read operations; the address is
latched on a Clock edge (rising or falling, accord-
ing to the configuration settings) when Latch En-
able is at V
IL
. Clock is don't care during
asynchronous read and in write operations.
Flash Wait (WAITF).
Wait is a Flash output signal
used during synchronous read to indicate whether
the data on the output bus are valid. This output is
high impedance when Flash Chip Enable is at V
IH
or Flash Reset is at V
IL
. It can be configured to be
active during the wait cycle or one clock cycle in
advance. The WAITF signal is not gated by Output
Enable.
SRAM Chip Enable (E1S, E2S).
The Chip En-
able inputs activate the SRAM memory control
logic, input buffers and decoders. E1S at V
IH
or
E2S at V
IL
deselects the memory and reduces the
power consumption to the standby level. E1S and
E2S can also be used to control writing to the
SRAM memory array, while WS remains at V
IL.
It
is not allowed to set EF at V
IL,
E1S at V
IL
and E2S
at V
IH
at the same time.
SRAM Write Enable (WS).
The Write Enable in-
put controls writing to the SRAM memory array.
WS is active low.
SRAM Output Enable (GS).
The Output Enable
gates the outputs through the data buffers during
a read operation of the SRAM memory. GS is ac-
tive low.
SRAM Upper Byte Enable (UBS).
The
Byte Enable input enables the upper byte for
SRAM (DQ8-DQ15). UBS is active low.
SRAM Lower Byte Enable (LBS).
The
Byte Enable input enables the lower byte for
SRAM (DQ0-DQ7). LBS is active low.
V
DDF
Supply Voltage.
V
DDF
provides the power
supply to the internal core of the Flash memory de-
Upper
Lower
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PDF描述 |
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| M36WT864B10ZA6T | 64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product |
| M36WT864BF | 64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product |
| M36WT864T10ZA6T | 64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product |
| M36WT864TF | 64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product |
| M36WT864B85ZA6T | 64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M36WT864TF | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product |
| M36WT864TF70ZA6T | 功能描述:組合存儲(chǔ)器 64M (4Mx16) 70ns RoHS:否 制造商:Microchip Technology 組織:512 K x 16 電源電壓-最大: 電源電壓-最小: 最大工作溫度:+ 85 C 最小工作溫度:- 20 C 封裝 / 箱體:LFBGA-48 封裝:Tray |
| M36WT864TFZA | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product |
| M36WT8B10ZA6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product |
| M36WT8B70ZA6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product |
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