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參數(shù)資料
| 型號： | M36WT864T85ZA6T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product |
| 中文描述： | 64兆位4Mb的x16插槽，多銀行，突發(fā)閃存和8兆位的SRAM為512k x16，內(nèi)存產(chǎn)品多 |
| 文件頁數(shù)： | 40/92頁 |
| 文件大小： | 624K |
| 代理商： | M36WT864T85ZA6T |
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M36WT864TF, M36WT864BF
40/92
SRAM OPERATIONS
There are five standard operations that control the
SRAM component. These are Bus Read, Bus
Write, Standby/Power-down, Data Retention and
Output Disable. A summary is shown in Table 2,
Main Operation Modes
Read.
Read operations are used to output the
contents of the SRAM Array. The data is output ei-
ther by x8 (DQ0-DQ7) or x16 (DQ0-DQ15) de-
pending on which of the LBS and UBS signals are
enabled. The SRAM is in Read mode whenever
Chip Enable, E2S, and Write Enable, WS, are at
V
IH
, and Output Enable, GS, and Chip Enable E1S
are at V
IL
.
Valid data will be available on the output pins after
a time of t
AVQV
after the last stable address. If the
Chip Enable or Output Enable access times are
not met, data access will be measured from the
limiting parameter (t
ELQV
, t
EHQV
, or t
GLQV
) rather
than the address. Data out may be indeterminate
at t
ELQX
, t
GLQX
and t
BLQX
, but data lines will al-
ways be valid at t
AVQV
(see Table 26, Figures 19
and 20).
Write.
Write operations are used to write data to
the SRAM. The SRAM is in Write mode whenever
Write Enable, WS, and Chip Enable, E1S, are at
V
IL
, and Chip Enable, E2S, is at V
IH
.
Either the Chip Enable input, E1S or the Write En-
able input, WS, must be deasserted during ad-
dress transitions for subsequent write cycles.
A Write operation is initiated when E1S is at V
IL
,
E2S is at V
IH
and WS is at V
IL
. When UBS or LBS
are Low, the data is latched on the falling edge of
E1S, or WS, whichever occurs first. When UBS or
LBS are High, the data is latched on the falling
edge of UBS, or LBS , whichever occurs first.
The Write cycle is terminated on the rising edge of
E1S, WS , UBS or LBS, whichever occurs first.
If the Output is enabled (E1S=V
IL
, E2S=V
IH
,
GS=V
IL
and UBS=LBS=V
IL
), then WS will return
the outputs to high impedance within t
WLQZ
of its
falling edge. Care must be taken to avoid bus con-
tention in this type of operation. The Data input
must be valid for t
DVWH
before the rising edge of
Write Enable, for t
DVEH
before the rising edge of
E1S or for t
DVBH
before the rising edge of UBS/
LBS, whichever occurs first, and remain valid for
t
WHDX
, t
EHDX
and t
BHDX
respectively.
(see Table 27, Figure 22, 23 and 24).
Standby/Power-Down
.
The SRAM component
has a chip enabled power-down feature which in-
vokes an automatic standby mode (see Table 26,
Figure 19). The SRAM is in Standby mode when-
ever either Chip Enable is deasserted, E1S at V
IH
or E2S at V
IL
.
Data Retention.
The SRAM data retention per-
formances as V
DDS
go down to V
DR
are described
in Table 28 and Figures 25 and 26. In E1S con-
trolled data retention mode, the minimum standby
current mode is entered when E1S
≥
V
DDS
– 0.2V
and E2S
≤
0.2V or E2S
≥
V
DDS
– 0.2V. In E2S
controlled data retention mode, minimum standby
current mode is entered when E2S
≤
0.2V.
Output Disable.
The SRAM is in the output dis-
able state when GS and WS are both at V
IH
, refer
to Table 2 for more details.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M36WT864B10ZA6T | 64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product |
| M36WT864BF | 64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product |
| M36WT864T10ZA6T | 64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product |
| M36WT864TF | 64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product |
| M36WT864B85ZA6T | 64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M36WT864TF | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product |
| M36WT864TF70ZA6T | 功能描述:組合存儲器 64M (4Mx16) 70ns RoHS:否 制造商:Microchip Technology 組織:512 K x 16 電源電壓-最大: 電源電壓-最小: 最大工作溫度:+ 85 C 最小工作溫度:- 20 C 封裝 / 箱體:LFBGA-48 封裝:Tray |
| M36WT864TFZA | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product |
| M36WT8B10ZA6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product |
| M36WT8B70ZA6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product |
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