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參數(shù)資料
| 型號： | M36W832Te85ZA6S |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 32 Mbit 2Mb x16, Boot Block Flash Memory and 8 Mbit 512Kb x16 SRAM, Multiple Memory Product |
| 中文描述： | 32兆位的2Mb x16插槽，引導(dǎo)塊閃存和8兆位的SRAM 512KB的x16，內(nèi)存產(chǎn)品多 |
| 文件頁數(shù)： | 25/64頁 |
| 文件大?。?/td> | 897K |
| 代理商： | M36W832TE85ZA6S |
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M36W832TE, M36W832BE
SRAM Operations
There are five standard operations that control the
SRAM component. These are Bus Read, Bus
Write, Standby/Power-down, Data Retention and
Output Disable. A summary is shown in Table 2,
Main Operation Modes
Read.
Read operations are used to output the
contents of the SRAM Array.
The SRAM is in Byte Read mode whenever Write
Enable, WS, is at V
IH
, Output Enable, GS, is at V
IL
,
Chip Enable, E1S, is at V
IL
, Chip Enable, E2S, is
at V
IH
, and UBS or LBS is at V
IL
.
The SRAM is in Word Read mode whenever Write
Enable, WS, is at V
IH
, Output Enable, GS, is at V
IL
,
Byte Enable inputs UBS and LBS are both at V
IL
and the two Chip Enable inputs, E1S, and E2S are
Don’t Care.
Valid data will be available on the output pins after
a time of t
AVQV
after the last stable address. If the
Chip Enable or Output Enable access times are
not met, data access will be measured from the
limiting parameter (t
E1LQV
, t
E2HQV
, or t
GLQV
) rath-
er than the address. Data out may be indetermi-
nate at t
E1LQX
, t
E2HQX
and t
GLQX
, but data lines
will always be valid at t
AVQV
(see Table 20, Figures
14 and 15).
Write.
Write operations are used to write data to
the SRAM. The SRAM is in Write mode whenever
IL
, and E2S is at V
IH
. Either
the Chip Enable inputs, E1S and E2S, or the Write
Enable input, WS, must be deasserted during ad-
dress transitions for subsequent write cycles.
A Write operation is initiated when E1S is at V
IL
,
E2S is at V
IH
and WS is at V
IL
. The data is latched
o the falling edge of E1S, the rising edge of E2S or
the falling edge of WS, whichever occurs last. The
Write cycle is terminated on the rising edge of
E1S, the rising edge of WS or the falling edge of
E2S, whichever occurs first.
If the Output is enabled (E1S=V
IL
, E2S=V
IH
and
GS=V
IL
), then WS will return the outputs to high
impedance within t
WLQZ
of its falling edge. Care
must be taken to avoid bus contention in this type
of operation. The Data input must be valid for t
D-
VWH
before the rising edge of Write Enable, for
t
DVE1H
before the rising edge of E1S or for t
DVE2L
before the falling edge of E2S, whichever occurs
first, and remain valid for t
WHDX
, t
E1HAX
or t
E2LAX
(see Table 21, Figure 17, 18, 19 and 20).
Standby/Power-Down.
The SRAM component
has a chip enabled power-down feature which in-
vokes an automatic standby mode (see Table 20
and Figure 16). The SRAM is in Standby mode
whenever either Chip Enable is deasserted, E1S
at V
IH
or E2S at V
IL
.
Data Retention.
The SRAM data retention per-
formance as V
DDS
goes down to V
DR
are de-
scribed in Table 22, Figures 21 and 22, SRAM
Low V
DDS
Data Retention AC Waveforms, E1S
Controlled and SRAM Low V
DDS
Data Retention
AC Waveforms, E2S Controlled, respectively.
Output Disable.
The data outputs are high im-
pedance when the Output Enable, GS, is at V
IH
with Write Enable, WS, at V
IH
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M36W832Te85ZA6T | 32 Mbit 2Mb x16, Boot Block Flash Memory and 8 Mbit 512Kb x16 SRAM, Multiple Memory Product |
| M36WT864 | 64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product |
| M36WT864B70ZA6T | 64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product |
| M36WT864T85ZA6T | 64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product |
| M36WT864B10ZA6T | 64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M36W832TE85ZA6T | 功能描述:組合存儲器 32M (2Mx16) 85ns RoHS:否 制造商:Microchip Technology 組織:512 K x 16 電源電壓-最大: 電源電壓-最小: 最大工作溫度:+ 85 C 最小工作溫度:- 20 C 封裝 / 箱體:LFBGA-48 封裝:Tray |
| M36W832TEZA | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Mbit 2Mb x16, Boot Block Flash Memory and 8 Mbit 512Kb x16 SRAM, Multiple Memory Product |
| M36W832TE-ZAT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Mbit 2Mb x16, Boot Block Flash Memory and 8 Mbit 512Kb x16 SRAM, Multiple Memory Product |
| M36W864BE-70ZA6 | 制造商:Micron Technology Inc 功能描述:64M FLASH, 8M SRAM, 3V, BOT, BGA, IND - Trays |
| M36W864TE-70ZA6 | 制造商:Micron Technology Inc 功能描述:64M FLASH, 8M SRAM, 3V, TOP, BGA, IND - Trays |
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