參數(shù)資料
型號: M36W832Te85ZA1S
廠商: 意法半導(dǎo)體
英文描述: 32 Mbit 2Mb x16, Boot Block Flash Memory and 8 Mbit 512Kb x16 SRAM, Multiple Memory Product
中文描述: 32兆位的2Mb x16插槽,引導(dǎo)塊閃存和8兆位的SRAM 512KB的x16,內(nèi)存產(chǎn)品多
文件頁數(shù): 37/64頁
文件大?。?/td> 897K
代理商: M36W832TE85ZA1S
37/64
M36W832TE, M36W832BE
Table 20. SRAM Read AC Characteristics
Note: 1. Sampled only. Not 100% tested.
Figure 17. SRAM Write AC Waveforms, E1
S
or E2S Controlled
Note: 1. DQ0-DQ15 are high impedance if GS = V
IH
.
2. If E1S or E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance.
Symbol
Alt
Parameter
SRAM
Unit
Min
Max
t
AVAV
t
RC
Read Cycle Time
70
ns
t
AVQV
t
ACC
Address Valid to Output Valid
70
ns
t
AXQX
t
OH
Address Transition to Output Transition
10
ns
t
E1HQZ
t
E2LQZ
t
CHZ1
Chip Enable 1 High to Output Hi-Z
25
ns
t
E1LQV
t
E2HQV
t
ACS1
Chip Enable 1 Low or Chip Enable 2 High to Output Valid
70
ns
t
E1LQX
t
E2HQX
t
CLZ1
Chip Enable 1 Low to Output Transition
10
ns
t
GHQZ
t
OHZ
Output Enable High to Output Hi-Z
25
ns
t
GLQV
t
OE
Output Enable Low to Output Valid
35
ns
t
GLQX
t
OLZ
Output Enable Low to Output Transition
5
ns
t
PD (1)
Chip Enable 1 High or Chip Enable 2 Low to Power Down
70
ns
t
PU (1)
Chip Enable 1 Low or Chip Enable 2 High to Power Up
0
ns
AI07966
tAVAV
tE1HAX
tDVE1H
tDVE2L
INPUT VALID
A0-A18
E1S
WS
DQ0-DQ15
ADDRESS VALID
E2S
tAVE1H
tAVE2L
tWLE1H
tWLE2L
tE1HDZ
tE2LDZ
tAVE1L
tE2HE2L
tE1LE1H
tAVE2H
tE2LAX
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