參數(shù)資料
型號: M36W0R6050T1ZAQF
元件分類: 存儲器
英文描述: SPECIALTY MEMORY CIRCUIT, PBGA88
封裝: 8 X 10 MM, 0.80 MM PITCH, ROHS COMPLIANT, TFBGA-88
文件頁數(shù): 3/22頁
文件大?。?/td> 428K
代理商: M36W0R6050T1ZAQF
M36W0R6050T1, M36W0R6050B1
Signal descriptions
11/22
2.12
PSRAM Chip Enable (E2P)
When de-asserted (Low), the Chip Enable input E2P, puts the device in Power-Down mode.
This is the lowest power mode according to the Configuration Register settings (see
M69KB048BD datasheet).
2.13
PSRAM Output Enable (GP)
The Output Enable, GP, provides a high speed tri-state control, allowing fast read/write
cycles to be achieved with the common I/O data bus.
2.14
PSRAM Write Enable (WP)
The Write Enable, WP, controls the Bus Write operation of the memory’s Command
Interface.
2.15
PSRAM Upper Byte Enable (UBP)
The Upper Byte Enable, UBP, gates the data on the Upper Byte Data Inputs/Outputs (DQ8-
DQ15) to or from the upper part of the selected address during a Write or Read operation.
2.16
PSRAM Lower Byte Enable (LBP)
The Lower Byte Enable, LBP, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-
DQ7) to or from the lower part of the selected address during a Write or Read operation.
2.17
VDDF supply voltage
VDDF provides the power supply to the internal core of the Flash memory component. It is
the main power supplies for all Flash memory operations (Read, Program and Erase).
2.18
VDDP supply voltage
The VDDP Supply Voltage supplies the power for all operations (Read or Write) and for
driving the refresh logic, even when the device is not being accessed.
2.19
VDDQF supply voltage
VDDQF provides the power supply for the Flash memory I/O pins. This allows all Outputs to
be powered independently of the Flash memory core power supply, VDDF.
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