- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄296383 > M36W0R6050T1ZAQF SPECIALTY MEMORY CIRCUIT, PBGA88 PDF資料下載
參數(shù)資料
| 型號(hào)： | M36W0R6050T1ZAQF |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA88 |
| 封裝： | 8 X 10 MM, 0.80 MM PITCH, ROHS COMPLIANT, TFBGA-88 |
| 文件頁(yè)數(shù)： | 2/22頁(yè) |
| 文件大?。?/td> | 428K |
| 代理商： | M36W0R6050T1ZAQF |
第1頁(yè)當(dāng)前第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)
Signal descriptions
M36W0R6050T1, M36W0R6050B1
10/22
2.6
Flash Write Protect (WPF)
Write Protect is an input that gives an additional hardware protection for each block. When
Write Protect is Low, VIL, Lock-Down is enabled and the protection status of the Locked-
Down blocks cannot be changed. When Write Protect is at High, VIH, Lock-Down is disabled
and the Locked-Down blocks can be locked or unlocked. (Refer to Lock Status Table in
M58WR064HT/B datasheet).
2.7
Flash Reset (RPF)
The Reset input provides a hardware reset of the memory. When Reset is at VIL, the
memory is in Reset mode: the outputs are high impedance and the current consumption is
reduced to the Reset Supply Current IDD2. Refer to the M58WR064HT/B datasheet, for the
value of IDD2. After Reset all blocks are in the Locked state and the Configuration Register is
reset. When Reset is at VIH, the device is in normal operation. Exiting Reset mode the
device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch
Enable is required to ensure valid data outputs.
The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied
to VRPH (refer to the M58WR064HT/B datasheet).
2.8
Flash Latch Enable (LF)
Latch Enable latches the address bits on its rising edge. The address latch is transparent
when Latch Enable is Low, VIL, and it is inhibited when Latch Enable is High, VIH. Latch
Enable can be kept Low (also at board level) when the Latch Enable function is not required
or supported.
2.9
Flash Clock (KF)
The Clock input synchronizes the Flash memory to the microcontroller during synchronous
read operations; the address is latched on a Clock edge (rising or falling, according to the
configuration settings) when Latch Enable is at VIL. Clock is don't care during Asynchronous
Read and in write operations.
2.10
Flash Wait (WAITF)
WAIT is a Flash output signal used during Synchronous Read to indicate whether the data
on the output bus are valid. This output is high impedance when Flash Chip Enable is at VIH
or Flash Reset is at VIL. It can be configured to be active during the wait cycle or one clock
cycle in advance. The WAITF signal is not gated by Output Enable.
2.11
PSRAM Chip Enable (E1P)
When asserted (Low), the Chip Enable, E1P, activates the memory state machine, address
buffers and decoders, allowing Read and Write operations to be performed. When de-
asserted (High), all other pins are ignored, and the device is automatically put in Standby
mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M36W832BE85ZA1S | SPECIALTY MEMORY CIRCUIT, PBGA66 |
| M381L1713FTM-CA2 | 16M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| M38220MCMFS | 50000 SYSTEM GATE 2.5 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN |
| M38220E1FP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38220E1FS | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M36W0R6050T3 | 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:64-Mbit (4 Mbits 】16, multiple bank, burst) Flash memory and 16-Mbit (1 Mbit 】16) or 32-Mbit (2 Mbits x16) PSRAM MCP |
| M36W0R6050T3ZAQE | 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:64-Mbit (4 Mbits 】16, multiple bank, burst) Flash memory and 16-Mbit (1 Mbit 】16) or 32-Mbit (2 Mbits x16) PSRAM MCP |
| M36W0R6050T3ZAQF | 制造商:Micron Technology Inc 功能描述:WIRELESS - Tape and Reel |
| M36W0R6050T4ZAQE | 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays 制造商:Micron Technology Inc 功能描述:IC FLASH PSRAM 96M |
| M36W0R6050T4ZAQF | 制造商:Micron Technology Inc 功能描述:WIRELESS - Tape and Reel |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。