參數(shù)資料
型號: M36D0R6040T0ZAIF
廠商: 意法半導體
英文描述: 64 Mbit (4Mb x16, Multiple Bank, Page) Flash Memory and 16 Mbit (1Mb x16) PSRAM, Multi-Chip Package
中文描述: 64兆位(4Mb的x16插槽,多銀行,頁)閃存和16兆位(最快1Mb × 16)移動存儲芯片,多芯片封裝
文件頁數(shù): 9/18頁
文件大小: 329K
代理商: M36D0R6040T0ZAIF
9/18
M36D0R6040T0, M36D0R6040B0
Table 2. Main Operating modes
Note: 1. X = Don't care.
2. L
F
can be tied to V
IH
if the valid address has been previously latched.
3. Depends on G
F
.
4. WAIT signal polarity is configured using the Set Configuration Register command. Refer to M58WR064F(T/B) datasheet for details.
Operation
E
F
G
P
W
P
L
F
RP
F
WAIT
F(4)
E1
P
E2
P
G
P
W
P
UB
P
LB
P
DQ15-DQ0
Flash Read
V
IL
V
IL
V
IH
V
IL(2)
V
IH
PSRAM must be disabled
Flash Data Out
Flash Write
V
IL
V
IH
V
IL
V
IL(2)
V
IH
Flash Data In
Flash Address
Latch
V
IL
X
V
IH
V
IL
V
IH
Flash Data Out
or Hi-Z
(3)
Flash Output
Disable
V
IL
V
IH
V
IH
X
V
IH
Any PSRAM mode is allowed
Flash Hi-Z
Flash Standby
V
IH
X
X
X
V
IH
Hi-Z
Flash Hi-Z
Flash Reset
X
X
X
X
V
IL
Hi-Z
Flash Hi-Z
PSRAM Read
Flash Memory must be disabled
V
IL
V
IH
V
IL
V
IH
V
IL
V
IL
PSRAM data
out
PSRAM Write
V
IL
V
IH
V
IH
V
IL
V
IL
V
IL
PSRAM data in
Output Disable
Any Flash mode is allowed.
V
IL
V
IH
V
IH
V
IH
X
X
PSRAM Hi-Z
PSRAM
Standby
V
IH
V
IH
X
X
X
X
PSRAM Hi-Z
PSRAM Deep
Power-Down
X
V
IL
X
X
X
X
PSRAM Hi-Z
相關PDF資料
PDF描述
M36D0R6040B0ZAIF 64 Mbit (4Mb x16, Multiple Bank, Page) Flash Memory and 16 Mbit (1Mb x16) PSRAM, Multi-Chip Package
M36D0R6040B0ZAIT 64 Mbit (4Mb x16, Multiple Bank, Page) Flash Memory and 16 Mbit (1Mb x16) PSRAM, Multi-Chip Package
M36D0R6040T0ZAI 64 Mbit (4Mb x16, Multiple Bank, Page) Flash Memory and 16 Mbit (1Mb x16) PSRAM, Multi-Chip Package
M36D0R6040T0 64 Mbit (4Mb x16, Multiple Bank, Page) Flash Memory and 16 Mbit (1Mb x16) PSRAM, Multi-Chip Package
M36D0R6040B0ZAIE 64 Mbit (4Mb x16, Multiple Bank, Page) Flash Memory and 16 Mbit (1Mb x16) PSRAM, Multi-Chip Package
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