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參數(shù)資料
| 型號(hào)： | M34584EDFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDSO42 |
| 封裝： | 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-42 |
| 文件頁數(shù)： | 48/157頁 |
| 文件大?。?/td> | 1130K |
| 代理商： | M34584EDFP |
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Skip condition
Datailed description
Carry
flag
CY
Rev.3.00
2004.08.06
page 141 of 155
REJ03B0010-0300Z
4584 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
–
V22 = 0: (ADF) = 1
–
(P) = 1
(WDF1) = 1
–
In the A/D conversion mode (Q13 = 0), transfers the high-order 4 bits (AD9–AD6) of register AD to register
B, and the middle-order 4 bits (AD5–AD2) of register AD to register A.
In the comparator mode (Q13 = 1), transfers the middle-order 4 bits (AD7–AD4) of register AD to register B,
and the low-order 4 bits (AD3–AD0) of register AD to register A.
(Q13: bit 3 of A/D control register Q1)
Transfers the low-order 2 bits (AD1, AD0) of register AD to the high-order 2 bits (AD3, AD2) of register A.
In the comparator mode (Q13 = 1), transfers the contents of register B to the high-order 4 bits (AD7–AD4) of
comparator register, and the contents of register A to the low-order 4 bits (AD3–AD0) of comparator register.
(Q13 = bit 3 of A/D control register Q1)
Clears (0) to A/D conversion completion flag ADF, and the A/D conversion at the A/D conversion mode (Q13
= 0) or the comparator operation at the comparator mode (Q13 = 1) is started.
(Q13 = bit 3 of A/D control register Q1)
When V22 = 0 : Skips the next instruction when A/D conversion completion flag ADF is “1.” After skipping,
clears (0) to the ADF flag. When the ADF flag is “0,” executes the next instruction. (V22: bit 2 of interrupt
control register V2)
Transfers the contents of A/D control register Q1 to register A.
Transfers the contents of register A to A/D control register Q1.
Transfers the contents of A/D control register Q2 to register A.
Transfers the contents of register A to A/D control register Q2.
Transfers the contents of A/D control register Q3 to register A.
Transfers the contents of register A to A/D control register Q3.
No operation; Adds 1 to program counter value, and others remain unchanged.
Puts the system in RAM back-up state by executing the POF instruction after executing the EPOF instruction.
Makes the immediate after POF instruction valid by executing the EPOF instruction.
Skips the next instruction when the P flag is “1”.
After skipping, the P flag remains unchanged.
Skips the next instruction when watchdog timer flag WDF1 is “1.” After skipping, clears (0) to the WDF1 flag.
Also, stops the watchdog timer function when executing the WRST instruction immediately after the DWDT
instruction.
Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction.
System reset occurs.
The voltage drop detection circuit is valid at RAM back-up mode when VDCE pin is “H”.
Sets referring data area to pages 0 to 63 when the TABP p instruction is executed.
This instruction is valid only for the TABP p instruction.
Sets referring data area to pages 64 to 127 when the TABP p instruction is executed.
This instruction is valid only for the TABP p instruction.
Transfers the high-order 4 bits (SI7–SI4) of register SI to register B, and transfers the low-order 4 bits (SI3–
SI0) of register SI to register A.
Transfers the contents of register B to the high-order 4 bits (SI7–SI4) of register SI, and transfers the con-
tents of register A to the low-order 4 bits (SI3–SI0) of register SI.
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