Rev.3.02
Dec 22, 2006
page 54 of 142
REJ03B0025-0302
4556 Group
Fig. 44 State transition
Fig. 45 Set source and clear source of the P flag
Fig. 46 Start condition identified example using the SNZP instruction
B
Operation state
Operation source clock: f(XIN)
Oscillation circuit:
Ceramic resonator
E
Clock operating mode
f(RING): stop
f(XIN): stop
f(XCIN): operating
Key-on wakeup
(Stabilizing time c )
POF2 instruction
execution
F
Power down mode
High-speed mode
D
Operation source clock:
f(XCIN)
Oscillation circuit:
Quartz-crystal oscillation
MR1, MR0
←00
MR1, MR0
←10
Low-speed mode
POF2 instruction
execution
Key-on wakeup
(Stabilizing time e )
POF instruction
execution
Key-on wakeup
(Stabilizing time e )
POF instruction
execution
Key-on wakeup
(Stabilizing time c )
CRCK instruction no execution
Operation state
Stabilizing time a : Microcomputer starts its operation after counting the f(RING) to 1376 times.
Stabilizing time b : Microcomputer starts its operation after counting the f(RING) to (system clock division ratio 15) times.
Stabilizing time c : Microcomputer starts its operation after counting the f(XIN) to (system clock division ratio 171) times.
Stabilizing time d : Microcomputer starts its operation after counting the f(XIN) to (system clock division ratio 15) times.
Stabilizing time e : Microcomputer starts its operation after counting the f(XCIN) to (system clock division ratio 171) times.
Reset
A
POF2 instruction
execution
Key-on wakeup
(Stabilizing time b )
POF instruction
execution
Key-on wakeup
(Stabilizing time b )
(Stabilizing time a )
Operation state
Operation source clock:
f(RING)
Oscillation circuit:
On-chip oscillator
C
POF2 instruction
execution
Key-on wakeup
(Stabilizing time d )
POF instruction
execution
Key-on wakeup
(Stabilizing time d )
Operation state
Operation source clock: f(XIN)
Oscillation circuit:
RC oscillation
f(RING): stop
f(XIN): stop
f(XCIN): stop
CRCK instruction execution
MR1, MR0
←00
MR1, MR0
←01
Internal mode
MR
1
,MR
0←
10
MR
1
,MR
0←
01
and generate the wait time until the oscillation is stabilized, and then, switch the system clock.
6: When the unoperating clock is selected as the system clock, turn it on by the clock control register RG,
If the CRCK instruction is not executed, the ceramic oscillation is selected as the main clock f(XIN).
5: When the RC oscillation circuit is used, executing the CRCK instruction is required.
Main clock (f(XIN)) and Suc-clock (f(XCIN)) are valid.
A ceramic oscillation is selected as the main clock (f(XIN)).
4: The state after system is released from reset;
3: Continuous execution of the EPOF instruction and the POF2 instruction is required to go into the RAM back-up state.
2: Continuous execution of the EPOF instruction and the POF instruction is required to go into the clock operating state.
Notes 1: Selection of the system clock by the clock control registers MR and RG is state retained at power down.
The waiting time to stabilize oscillation at return can be adjustment by setting the clock control registers MR and
RG before transition to the power down state.
S
R
Q
Power down flag P
POF or
POF2
instruction
Reset input
q Set source
q Clear source
Reset input
EPOF instruction +
POF or
POF2
instruction
EPOF instruction +
Program start
P = “1”
?
Yes
Warm start
Cold start
No
T3F = “1”
?
Yes
No
Return from
timer 3 underflow
Return from
external wakeup signal