參數(shù)資料
型號: M34554EDFP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP64
封裝: 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64
文件頁數(shù): 61/140頁
文件大小: 1079K
代理商: M34554EDFP
Rev.3.00
Aug 06, 2004
page 25 of 136
REJ03B0043-0300Z
4554 Group
Fig. 16 Interrupt sequence
T1F,T2F,T3F,
T4F,T5F
INT0,INT1
EXF0,EXF1
T1
T2
T3
T1
T2
T3
T2
T3
T1
T2
T3
T1
T2
q When an interrupt request flag is set after its interrupt is enabled (Note 1)
System clock
(STCK)
The program starts
from the interrupt
address.
Interrupt enabled state
1 machine cycle
EI instruction execution cycle
Interrupt enable
flag (INTE)
Retaining level of system
clock for 4 periods or more
is necessary.
Interrupt disabled state
External
interrupt
Timer 1,
Timer 2,
Timer 3,
Timer 4,
Timer 5
interrupts
Interrupt activated
condition is satisfied.
Notes 1: The address is stacked to the last cycle.
2: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied.
Flag cleared
2 to 3 machine cycles
(Notes 1, 2)
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