參數(shù)資料
型號: M34554EDFP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP64
封裝: 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64
文件頁數(shù): 32/140頁
文件大?。?/td> 1079K
代理商: M34554EDFP
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Datailed description
Carry
flag
CY
Rev.3.00
Aug 06, 2004
page 125 of 136
REJ03B0043-0300Z
4554 Group
(P) = 1
(WDF1) = 1
Transfers the contents of key-on wakeup control register K0 to register A.
Transfers the contents of register A to key-on wakeup control register K0.
Transfers the contents of key-on wakeup control register K1 to register A.
Transfers the contents of register A to key-on wakeup control register K1.
Transfers the contents of key-on wakeup control register K2 to register A.
Transfers the contents of register A to key-on wakeup control register K2.
Transferts the contents of register A to port output format control register FR0.
Transferts the contents of register A to port output format control register FR1.
Transferts the contents of register A to port output format control register FR2.
Transfers the contents of LCD control register L1 to register A.
Transfers the contents of register A to LCD control register L1.
Transfers the contents of register A to LCD control register L2.
Transfers the contents of register A to LCD control register L3.
Selects the ceramic resonator for main clock, stops the on-chip oscillator (internal oscillator).
Selects the RC oscillation circuit for main clock, stops the on-chip oscillator (internal oscillator).
Transfers the contents of clock control regiser MR to register A.
Transfers the contents of register A to clock control register MR.
No operation; Adds 1 to program counter value, and others remain unchanged.
Puts the system in clock operating mode by executing the POF instruction after executing the EPOF instruction.
Puts the system in RAM back-up state by executing the POF2 instruction after executing the EPOF instruction.
Makes the immediate after POF or POF2 instruction valid by executing the EPOF instruction.
Skips the next instruction when the P flag is “1”.
After skipping, the P flag remains unchanged.
Skips the next instruction when watchdog timer flag WDF1 is “1.” After skipping, clears (0) to the WDF1 flag.
Also, stops the watchdog timer function when executing the WRST instruction immediately after the DWDT
instruction.
Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction.
Sets referring data area to pages 0 to 63 when the TABP p instruction is executed.
This instruction is valid only for the TABP p instruction.
Sets referring data area to pages 64 to 127 when the TABP p instruction is executed.
This instruction is valid only for the TABP p instruction.
Validates the voltage drop detection circuit at power down (clock operating mode and RAM back-up mode)
when VDCE pin is “H”.
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