參數(shù)資料
型號： M34554EDFP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP64
封裝： 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64
文件頁數(shù)： 60/140頁
文件大小： 1079K
代理商： M34554EDFP
Rev.3.00
Aug 06, 2004
page 24 of 136
REJ03B0043-0300Z
4554 Group
(6) Interrupt control registers
Interrupt control register V1
Interrupt enable bits of external 0, external 1, timer 1 and timer 2
are assigned to register V1. Set the contents of this register
through register A with the TV1A instruction. The TAV1 instruction
can be used to transfer the contents of register V1 to register A.
Table 6 Interrupt control registers
Note: “R” represents read enabled, and “W” represents write enabled.
(7) Interrupt sequence
Interrupts only occur when the respective INTE flag, interrupt en-
able bits (V10–V13, V20, V21, V23), and interrupt request flag are
“1.” The interrupt actually occurs 2 to 3 machine cycles after the
cycle in which all three conditions are satisfied. The interrupt oc-
curs after 3 machine cycles only when the three interrupt
conditions are satisfied on execution of other than one-cycle in-
structions (Refer to Figure 16).
V13
V12
V11
V10
Interrupt control register V1
Timer 2 interrupt enable bit
Timer 1 interrupt enable bit
External 1 interrupt enable bit
External 0 interrupt enable bit
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid)
Interrupt disabled (SNZ1 instruction is valid)
Interrupt enabled (SNZ1 instruction is invalid)
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
0
1
0
1
0
1
0
1
at power down : 00002
at reset : 00002
R/W
TAV1/TV1A
Interrupt disabled (SNZT4 instruction is valid)
Interrupt enabled (SNZT4 instruction is invalid)
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZT5 instruction is valid)
Interrupt enabled (SNZT5 instruction is invalid)
Interrupt disabled (SNZT3 instruction is valid)
Interrupt enabled (SNZT3 instruction is invalid)
Timer 4 interrupt enable bit
Not used
Timer 5 interrupt enable bit
Timer 3 interrupt enable bit
Interrupt control register V2
at power down : 00002
at reset : 00002
0
1
0
1
0
1
0
1
R/W
TAV2/TV2A
Interrupt control register V2
The timer 3, timer 5, timer 4 interrupt enable bit is assigned to
register V2. Set the contents of this register through register A
with the TV2A instruction. The TAV2 instruction can be used to
transfer the contents of register V2 to register A.
V23
V22
V21
V20
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