參數(shù)資料
型號： M34551E8-XXXFP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, OTPROM, MICROCONTROLLER, PQFP48
封裝： 7 X 10 MM, 0.65 MM PITCH, PLASTIC, QFP-48
文件頁數(shù)： 20/154頁
文件大小： 1778K
代理商： M34551E8-XXXFP
APPLICATION
2-39
4551 Group User’s Manual
2.6 Power down function
The 4551 Group has the clock operation mode and RAM back-up mode for the power down function. The
4551 Group enters 12 kinds of state which includes the reset state to reduce the power dissipation. Figure
2.6.1 shows the state transition, and Figure 2.6.2 shows the oscillation stabilizing time.
In this section, the clock control function, each power down function, related register and application example
for the power down function are described.
Fig. 2.6.1 State transition
Stabilizing time a : An interval required to stabilize the f(X IN) oscillation is automatically generated by hardware.
Stabilizing time b : An interval required to stabilize the f(X CIN) oscillation is automatically generated by hardware.
Stabilizing time c : Generate an interval required to stabilize the f(X IN) oscillation in state C or G by software at the
transition D
→C, D→G, H→C, H→G, J→C, or J→G.
Stabilizing time d : Generate an interval required to stabilize the f(X CIN) oscillation in state B, F by software at the
transition A
→B, E→F, A→F, or E→B.
Return input 1: External wakeup signal (P0 0–P03, P10–P13)
Return input 2: Timer 2 interrupt request flag
Notes 1. MR3=“1”
→The microcomputer starts its operation after counting f(X CIN) clock signal 59 to 70 times.
MR3=“0”
→The microcomputer starts its operation after counting f(X CIN) clock signal 32 to 43 times.
2. When the following 2 conditions are satisfied, the transition A
→E, B→F, A→F, C→F, G→F represented
by “
” can be executed.
(1) VDD = 2.2 V to 5.5 V (One Time PROM version: V DD = 2.5 V to 5.5 V), f(X IN)
≤ 1.0 MHz
(2) VDD = 4.5 V to 5.5 V, f(X IN)
≤ 2.0 MHz
MR
0
←
0
B
MR
0
←
1
C
MR
1
←
1
MR
1
←
0
D
K
A
MR
2
←
1
MR
0
←
0
F
MR
0
←
1
G
MR
1
←
1
MR
1
←
0
H
MR
2
←
0
E
MR
2
←
1
MR3
← 1
MR3
← 0
MR3
← 1
MR3
← 0
MR3
← 1
MR3
← 0
MR3
← 1
MR3
← 0
(Note 2)
(Stabilizing
time
c
)
J
f(XIN):Stop
f(XCIN) :
Oscillation
I
(Stabilizing
time
c )
(Stabilizing
time
d )(Stabilizing
time
d )
B , F
C , G
D , H
B , F
C , G
D , H
A , E
B , F
C , G
D , H
B , F
C , G
D , H
A , E
(Note 2)
Reset
POF execution
Return input 1
(Stabilizing time a )
POF execution
Return input 1, 2
(Stabilizing time a )
POF execution
Return input 1, 2
(Stabilizing time c )
(Note 1)
Clock
operating
mode
POF execution
Return input 1, 2
(Stabilizing time c )
(Note 1)
f(XIN):Stop
f(XCIN):Stop
Clock
operating
mode
f(XIN):Oscillation
f(XCIN):Stop
System clock;
f(XIN)/4
MR=(10002)
MR
2
←
0
f(X
IN
):Oscillation
f(XCIN):Oscillation
f(XIN):Oscillation
f(XCIN):Oscillation
f(XIN):Stop
f(XCIN):Oscillation
System clock;
f(XIN)/4
MR=(11002)
System clock;
f(XCIN)/4
MR=(11012)
System clock;
f(XCIN)/4
MR=(11112)
f(XIN):Oscillation
f(XCIN):Stop
System clock;
f(XIN)
MR=(00002)
f(XIN):Oscillation
f(XCIN):Oscillation
System clock;
f(XIN)
MR=(01002)
f(XIN):Oscillation
f(XCIN):Oscillation
System clock;
f(XCIN)
MR=(01012)
f(XIN):Stop
f(XCIN):Oscillation
System clock;
f(XCIN)
MR=(01112)
(Stabilizing
time
d
)
(Note 2)
POF2 execution
Return input 1
(Stabilizing time a )
POF2 execution
Return input 1
(Stabilizing time a )
POF2 execution
Return input 1
(Stabilizing time b )
POF2 execution
Return input 1
(Stabilizing time b )
f(XIN):Stop
f(XCIN):Stop
RAM
back-up
mode
A , E
MR
2 ←
0
MR
3 ←
0
MR
2 ←
1
MR
3 ←
1
(Note 2)
MR
2
←
1
MR
2
←
0
MR
3
←
0
MR
3
←
1
MR
3
←
1
MR
0
←
0
MR
3
←
0
MR
0
←
1
MR
0 ←
1
MR
0 ←
0
MR
3 ←
1
MR
3 ←
0
MR
3
←
1
MR
1
←
0
MR
3
←
0
MR
1
←
1
MR
1 ←
0
MR
3 ←
0
MR
1 ←
1
MR
3 ←
1
(Stabilizing
time
c )
(Stabilizing
time
d
)
(Stabilizing
time
c
)
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