Rev.2.00
Aug 28, 2006
page 13 of 119
7643 Group
REJ03B0054-0200
Fig. 10 Memory map of special function register (SFR)
CPU mode register A (CPUA)
CPU mode register B (CPUB)
Interrupt request register A (IREQA)
Interrupt request register B (IREQB)
Interrupt request register C (IREQC)
Interrupt control register A (ICONA)
Interrupt control register B (ICONB)
Interrupt control register C (ICONC)
Port P0 (P0)
Port P0 direction register (P0D)
Port P1 (P1)
Port P1 direction register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Port P3 direction register (P3D)
Port control register (PTC)
Interrupt polarity select register (IPOL)
Port P2 pull-up control register (PUP2)
USB control register (USBC)
Port P6 (P6)
Port P6 direction register (P6D)
Port P5 (P5)
Port P5 direction register (P5D)
Port P4 (P4)
Port P4 direction register (P4D)
Port P7 (P7)
Port P7 direction register (P7D)
Port P8 (P8)
Port P8 direction register (P8D)
Reserved (Note 1)
Clock control register (CCR)
Reserved (Note 1)
Timer 1 (T1)
Timer 2 (T2)
Timer 3 (T3)
Reserved (Note 1)
Timer 123 mode register (T123M)
Serial I/O shift register (SIOSHT)
Serial I/O control register 1 (SIOCON1)
Serial I/O control register 2 (SIOCON2)
Reserved (Note 1)
UART mode register (UMOD)
UART baud rate generator (UBRG)
UART status register (USTS)
UART control register (UCON)
UART transmit/receive buffer register 1 (UTRB1)
UART transmit/receive buffer register 2 (UTRB2)
UART RTS control register (URTSC)
Reserved (Note 1)
000016
000116
000316
000416
000216
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
Reserved (Note 1)
DMAC index and status register (DMAIS)
DMAC channel x mode register 1 (DMAx1)
DMAC channel x mode register 2 (DMAx2)
DMAC channel x source register Low (DMAxSL)
DMAC channel x source register High (DMAxSH)
DMAC channel x destination register Low (DMAxDL)
DMAC channel x destination register High (DMAxDH)
DMAC channel x transfer count register Low (DMAxCL)
DMAC channel x transfer count register High (DMAxCH)
Reserved (Note 1)
USB address register (USBA)
USB power management register (USBPM)
USB interrupt status register 1 (USBIS1)
USB interrupt status register 2 (USBIS2)
USB interrupt enable register 1 (USBIE1)
USB interrupt enable register 2 (USBIE2)
Reserved (Note 1)
USB endpoint index register (USBINDEX)
USB endpoint x IN control register (IN_CSR)
USB endpoint x OUT control register (OUT_CSR)
USB endpoint x IN max. packet size register (IN_MAXP)
USB endpoint x OUT max. packet size register (OUT_MAXP)
USB endpoint x OUT write count register (WRT_CNT)
Reserved (Note 1)
USB endpoint FIFO mode register (USBFIFOMR)
USB endpoint 0 FIFO (USBFIFO0)
USB endpoint 1 FIFO (USBFIFO1)
USB endpoint 2 FIFO (USBFIFO2)
Reserved (Note 1)
Flash memory control register (FMCR) (Note 2)
Reserved (Note 1)
Frequency synthesizer control register (FSC)
Frequency synthesizer multiply register 1 (FSM1)
Frequency synthesizer multiply register 2 (FSM2)
Frequency synthesizer divide register (FSD)
003816
003916
003B16
003C16
003A16
003D16
003E16
003F16
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
FFC916 ROM code protect control register (ROMCP) (Note 3)
Notes 1: Do not write any data to this addresses, because these areas are reserved.
2: This area is reserved in the mask ROM version.
3: This area is on the ROM in the mask ROM version.