參數(shù)資料
型號： M34501M4-XXXFP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, MICROCONTROLLER, PDSO20
封裝： 5.30 X 12.60 MM, 1.27 MM PITCH, PLASTIC, SOP-20
文件頁數(shù)： 66/116頁
文件大?。?/td> 859K
代理商： M34501M4-XXXFP
4501 Group
Rev.3.01
2005.02.07
page 53 of 112
REJ03B0104-0301
CONTROL REGISTERS
I13
I12
I11
I10
INT pin input control bit (Note 3)
Interrupt valid waveform for INT pin/
return level selection bit (Note 3)
INT pin edge detection circuit control bit
INT pin
timer 1 control enable bit
Interrupt control register I1
R/W
at RAM back-up : state retained
at reset : 00002
INT pin input disabled
INT pin input enabled
Falling waveform (“L” level of INT pin is recognized with the SNZI0
instruction)/“L” level
Rising waveform (“H” level of INT pin is recognized with the SNZI0
instruction)/“H” level
One-sided edge detected
Both edges detected
Disabled
Enabled
0
1
0
1
0
1
0
1
MR3
Clock control register MR
System clock
f(XIN) (high-speed mode)
f(XIN)/2 (middle-speed mode)
f(XIN)/4 (low-speed mode)
f(XIN)/8 (default mode)
This bit has no function, but read/write is enabled.
at reset : 11002
at RAM back-up : 11002
MR3
0
1
R/W
Not used
System clock selection bits
0
1
0
1
MR2
0
1
0
1
MR1
MR0
MR2
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZAD instruction is valid)
Interrupt enabled (SNZAD instruction is invalid) (Note 2)
This bit has no function, but read/write is enabled.
R/W
V13
V12
V11
V10
V23
V22
V21
V20
Not used
A/D interrupt enable bit
Not used
Interrupt control register V2
at RAM back-up : 00002
at reset : 00002
0
1
0
1
0
1
0
1
Interrupt control register V1
Timer 2 interrupt enable bit
Timer 1 interrupt enable bit
Not used
External 0 interrupt enable bit
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid) (Note 2)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid) (Note 2)
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid) (Note 2)
0
1
0
1
0
1
0
1
R/W
at RAM back-up : 00002
at reset : 00002
R/W
at RAM back-up : 00002
at reset : 00002
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: These instructions are equivalent to the NOP instruction.
3: When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 in-
struction when the bit 0 (V10) of register V1 to “0”. In this time, set the NOP instruction after the SNZ0 instruction, for the case when a skip is
performed with the SNZ0 instruction.
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