- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄69010 > M34501M4-XXXFP 4-BIT, MROM, MICROCONTROLLER, PDSO20 PDF資料下載
參數(shù)資料
| 型號(hào)： | M34501M4-XXXFP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, MICROCONTROLLER, PDSO20 |
| 封裝： | 5.30 X 12.60 MM, 1.27 MM PITCH, PLASTIC, SOP-20 |
| 文件頁(yè)數(shù)： | 53/116頁(yè) |
| 文件大小： | 859K |
| 代理商： | M34501M4-XXXFP |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)當(dāng)前第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)
4501 Group
Rev.3.01
2005.02.07
page 41 of 112
REJ03B0104-0301
RAM BACK-UP MODE
The 4501 Group has the RAM back-up mode.
When the POF or POF2 instruction is executed continuously after
the EPOF instruction, system enters the RAM back-up state.
The POF or POF2 instruction is equal to the NOP instruction when
the EPOF instruction is not executed before the POF or POF2 in-
struction.
As oscillation stops retaining RAM, the function of reset circuit and
states at RAM back-up mode, current dissipation can be reduced
without losing the contents of RAM.
In the RAM back-up mode by the POF instruction, system enters
the RAM back-up mode and the voltage drop detection cicuit keeps
operating.
In the RAM back-up mode by the POF2 instruction, all internal
periperal functions stop.
Table 15 shows the function and states retained at RAM back-up.
Figure 39 shows the state transition.
(1) Identification of the start condition
Warm start (return from the RAM back-up state) or cold start (re-
turn from the normal reset state) can be identified by examining the
state of the power down flag (P) with the SNZP instruction.
(2) Warm start condition
When the external wakeup signal is input after the system enters
the RAM back-up state by executing the EPOF instruction and
POF or POF2 instruction continuously, the CPU starts executing
the program from address 0 in page 0. In this case, the P flag is
“1.”
(3) Cold start condition
The CPU starts executing the program from address 0 in page 0
when;
reset pulse is input to RESET pin, or
reset by watchdog timer is performed, or
voltage drop detection circuit is detected by the voltage drop
In this case, the P flag is “0.”
Table 15 Functions and states retained at RAM back-up
Function
Program counter (PC), registers A, B,
carry flag (CY), stack pointer (SP) (Note 2)
Contents of RAM
Port level
Selected oscillation circuit
Timer control register W1
Timer control registers W2, W6
Clock control register MR
Interrupt control registers V1, V2
Interrupt control register I1
Timer 1 function
Timer 2 function
A/D conversion function
Voltage drop detection circuit
A/D control register Q1
Pull-up control registers PU0 to PU2
Key-on wakeup control registers K0 to K2
External 0 interrupt request flag (EXF0)
Timer 1 interrupt request flag (T1F)
Timer 2 interrupt request flag (T2F)
Watchdog timer flags (WDF1)
Watchdog timer enable flag (WEF)
16-bit timer (WDT)
A/D conversion completion flag (ADF)
Interrupt enable flag (INTE)
POF2
O
(Note 6)
O
O
O
(Note 3)
O
(Note 3)
(Note 4)
(Note 4)
Notes 1: “O” represents that the function can be retained, and “” repre-
sents that the function is initialized.
Registers and flags other than the above are undefined at RAM
back-up, and set an initial value after returning.
2: The stack pointer (SP) points the level of the stack register and is
initialized to “7” at RAM back-up.
3: The state of the timer is undefined.
4: Initialize the watchdog timer flag WDF1 with the WRST instruction,
and then execute the POF or POF2 instruction.
5: This function is operating in the RAM back-up mode. When the
voltage drop is detected, system reset occurs.
6: As for the D2/C pin, the output latch of port C is set to “1” at the
RAM back-up. However, the output latch of port D2 is retained.
As for the other ports, their output levels are retained at the RAM
back-up.
RAM back-up
POF
O
(Note 6)
O
O
O
(Note 3)
O (Note 5)
O
(Note 3)
(Note 4)
(Note 4)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M34501E4FP | 4-BIT, OTPROM, MICROCONTROLLER, PDSO20 |
| M34502M2-XXXFP | 4-BIT, MROM, MICROCONTROLLER, PDSO24 |
| M34502M4-XXXFP | 4-BIT, MROM, MICROCONTROLLER, PDSO24 |
| M34506M4-XXXFP | 4-BIT, MROM, MICROCONTROLLER, PDSO20 |
| M34506E4FP | 4-BIT, OTPROM, MICROCONTROLLER, PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M34502E4 | 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34502E4FP | 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES |
| M34502M2 | 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34502M2-XXXFP | 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34502M4 | 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。