APPLICATION
2.3 Timers
2-22
4501 Group User’s Manual
2.3.2 Related registers
(1)
Interrupt control register V1
The external 0 interrupt enable bit is assigned to bit 0, timer 1 interrupt enable bit is assigned to bit
2, and the timer 2 interrupt enable bit is assigned to bit 3.
Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction
can be used to transfer the contents of register V1 to register A.
Table 2.3.1 shows the interrupt control register V1.
Table 2.3.1 Interrupt control register V1
Interrupt control register V1
at reset : 00002
at RAM back-up : 00002
R/W
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid) (Note 2)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid) (Note 2)
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid) (Note 2)
Timer 2 interrupt enable bit
Timer 1 interrupt enable bit
Not used
External 0 interrupt enable bit
V13
V12
V11
V10
0
1
0
1
0
1
0
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: These instructions are equivalent to the NOP instruction.
3: When timer is used, V11 and V10 are not used.
(2)
Timer control register W1
The timer 1 count start synchronous circuit control bit is assigned to bit 0, the timer 1 control bit is
assigned to bit 1, the prescaler dividing ratio selection bit is assigned to bit 2, and the prescaler
control bit is assigned to bit 3.
Set the contents of this register through register A with the TW1A instruction. The TAW1 instruction
can be used to transfer the contents of register W1 to register A.
Table 2.3.2 shows the timer control register W1.
Table 2.3.2 Timer control register W1
Timer control register W1
at reset : 00002
at RAM back-up : 00002
R/W
Stop (state initialized)
Operating
Instruction clock divided by 4
Instruction clock divided by 16
Stop (state retained)
Operating
Count start synchronous circuit not selected
Count start synchronous circuit selected
Prescaler control bit
Prescaler dividing ratio selection
bit
Timer 1 control bit
Timer 1 count start synchronous
circuit control bit
W13
W12
W11
W10
0
1
0
1
0
1
0
1
Note: “R” represents read enabled, and “W” represents write enabled.